Method for manufacturing semiconductor device

ABSTRACT

An object is to provide a highly reliable semiconductor device that is reduced in thickness and size and has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device at low cost and with high productivity. With the use of a conductive shield covering a semiconductor integrated circuit, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method. In addition, a semiconductor device can be formed at low cost with high productivity because a plating method is used for the formation of the conductive shield.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method formanufacturing the semiconductor device.

2. Description of the Related Art

In a semiconductor device (also referred to as a wireless signalprocessing unit, a semiconductor integrated circuit chip, or an IC chip)that sends and receives data by wireless communication through anantenna, breakdown (electrostatic breakdown) of the semiconductor devicedue to electrostatic discharge from the outside is a serious problemthat leads to decrease in reliability and productivity from amanufacturing process time of the semiconductor device to inspection andthe use as a product, and a measure against the problem is reported(e.g., see Reference 1).

In Reference 1, an example is described in which a conductive polymerlayer is used for a substrate or an adhesive in the aforementionedsemiconductor device to prevent electrostatic breakdown.

[Reference]

Reference 1: Japanese Published Patent Application No. 2007-241999

As the market of the aforementioned semiconductor devices expands,various shapes and various required characteristics are needed.Therefore, a semiconductor device which has high tolerance toelectrostatic breakdown and required characteristics is needed.

In the aforementioned semiconductor device in which reduction in sizeand thickness is achieved, it is also important to increase the strengthagainst external stress.

SUMMARY OF THE INVENTION

Therefore, an object is to provide a highly reliable semiconductordevice that is reduced in thickness and size and has tolerance toexternal stress and electrostatic discharge. Another object is toprevent defective shapes and defective characteristics due to theexternal stress or an electrostatic discharge in the manufacturingprocess, and to manufacture a semiconductor device with high yield.Still another object is to manufacture a semiconductor device at lowcost and with high productivity.

A semiconductor device according one embodiment of the present inventionincludes an antenna and a pair of insulators between which asemiconductor integrated circuit that is electrically connected to theantenna is sandwiched, and at least two conductive shields are providedby a plating method on outer sides of the insulators (on the sides wherethe semiconductor integrated circuit is not provided). In an embodimentof the present invention, the at least two conductive shields are formedso that at least the conductive shield on the top surface iselectrically connected to the conductive shield on the bottom surface.

The conductive shield may be formed by a plating method to cover theentire periphery (a top surface, a bottom surface, and side surfaces) ofthe semiconductor device (to wrap the semiconductor device), or aconductive region that electrically connects the pair of conductiveshields provided on the outer sides of the insulators may be formed. Theconductive region may be part of the side surface of the semiconductordevice or may be an electrode layer that penetrates inside thesemiconductor device. Note that the side surface of the semiconductordevice refers to a cut surface (divided surface) that is generated whena plurality of semiconductor integrated circuit chips provided on thesame insulator is cut (divided) into individual chips. The entire cutsurface or part of the cut surface may be covered with the conductiveshield.

A semiconductor device according to one embodiment of the presentinvention is a wireless signal processing unit which has functions ofsending and receiving signals to/from an external device by wirelesscommunication. Therefore, the conductive shield transmits anelectromagnetic wave that the antenna included in the semiconductordevice should send and receive, and prevents external static electricityfrom being applied to the semiconductor integrated circuit in thesemiconductor device.

The conductive shield diffuses static electricity applied byelectrostatic discharge to dissipate it or prevents local electriccharges (localization of electric charges) (prevents local potentialdifference) so that electrostatic breakdown of the semiconductorintegrated circuit can be prevented. The conductive shield is formed soas to cover (overlap) both surfaces of the semiconductor integratedcircuit with the insulator interposed therebetween.

Note that the conductive shield is not electrically connected to theantenna and the semiconductor integrated circuit.

Such a conductive shield is formed using a material to a thickness totransmit the electromagnetic wave that should be sent and received bythe sandwiched antenna and semiconductor integrated circuit and toprevent static electricity. Thus, a semiconductor device which hastolerance to electrostatic breakdown and has high reliability and whichcan send and receive data by wireless communication through the antennacan be provided.

The semiconductor integrated circuit is sandwiched between a pair ofinsulators. The pair of insulators also functions as an impactresistance layer against force (also referred to as external stress)externally given to the semiconductor device or as an impact diffusionlayer that diffuses the force. Provision of the insulators can reduceforce that is locally applied; therefore, damage, deterioration ofcharacteristics, or the like of the semiconductor device due to theexternal stress can be prevented.

In the semiconductor device, the semiconductor integrated circuit issandwiched between the pair of insulators. The semiconductor integratedcircuit is formed over a substrate, bonded to the insulator, and thenseparated from the substrate. In this specification, a surface of thesemiconductor integrated circuit that is formed by separation of thesemiconductor integrated circuit from the substrate is referred to as aseparation surface.

The conductive shield may have conductivity, and a conductive layerformed using a conductive material can be used. In an embodiment of thepresent invention, the conductive layer which is used for the conductiveshield is formed using a film including metal by a plating method.

A wet plating method by which a film including metal is formed byreducing metal ions that exist in an aqueous solution by electrons isused as a method for forming the conductive shield. When the wet platingmethod is classified in terms of a reduction method, there are areduction method by electricity (electrolytic (electric) platingmethod), a reduction method by a reducing agent (electroless platingmethod), a reduction method by using a difference of an ionizationtendency (displacement plating method), and the like. In an embodimentof the present invention, the aforementioned wet plating method can beused, and a combination of the aforementioned wet plating methods may beused.

A film can be formed isotropically with respect to an object by a wetplating method; therefore, a region where the film can be formed islarge, and a conductive shield that covers a periphery (a top surface, abottom surface, and side surfaces) of a semiconductor device can beformed in one plating process. The conductive shield formed in oneplating process can be a continuous film.

By a plating method, a region that can be treated at a time can belarge, productivity can be improved, and cost for a process can bereduced to achieve low cost. Therefore, when a conductive shield isformed by using a plating method, a semiconductor device of anembodiment of the present invention can be formed with high productivityat low cost. Lower cost of a process allows a semiconductor device to beprovided at lower cost.

As a conductive shield, a film of metal, a metal alloy, or the like, ora stacked layer of these can be used. The thickness of the conductiveshield may be more than 0 nm and less than or equal to about 1 μm.

In addition, a protective layer may be stacked over the conductiveshield. Even when the conductive shield is provided on the surface ofthe semiconductor device, the protective layer serves as an outermostsurface; therefore, deterioration of the conductive shield can beprevented.

For the insulator, a structure body in which a fibrous body isimpregnated with an organic resin can be used.

Alternatively, a material which has a low modulus of elasticity and highbreaking strength may be used as the insulator.

The insulator is preferably formed using a high-strength material. Astypical examples of the high-strength material, a polyvinyl alcoholresin, a polyester resin, a polyamide resin, a polyethylene resin, anaramid resin, a polyparaphenylenebenzobisoxazole resin, a glass resin,and the like can be given. When an insulator formed using ahigh-strength material having elasticity is provided, load such as localpressure is diffused and absorbed through the entire layer; therefore,the semiconductor device can be prevented from being damaged.

More specifically, as the insulator, an aramid resin, a polyethylenenaphthalate (PEN) resin, a polyethersulfone (PES) resin, a polyphenylenesulfide (PPS) resin, a polyimide (PI) resin, or the like can be used.

In this specification, the word “transfer” (also referred to astranspose) means that a semiconductor integrated circuit formed over onesubstrate is separated from the substrate and moved to anothersubstrate. In other words, it means that a place where the semiconductorintegrated circuit is provided is changed to another substrate.

A method for manufacturing a semiconductor device, according to anembodiment of the present invention, includes a step of forming asemiconductor integrated circuit and an antenna electrically connectedto the semiconductor integrated circuit; a step of sandwiching thesemiconductor integrated circuit and the antenna between a firstinsulator and a second insulator which are provided to face each other;and a step of forming, by a plating method, at least two conductiveshields that are electrically connected to each other on surfaces of thefirst insulator and the second insulator, on which the semiconductorintegrated circuit is not formed.

A method for manufacturing a semiconductor device, according to anembodiment of the present invention, includes a step of forming asemiconductor integrated circuit and an antenna electrically connectedto the semiconductor integrated circuit; a step of sandwiching thesemiconductor integrated circuit and the antenna between a firstinsulator and a second insulator which are provided to face each other;and a step of immersing a stack of the semiconductor integrated circuit,the antenna, the first insulator, and the second insulator in a platingsolution including a conductive material to form a conductive shieldcovering a surface of the stack.

A method for manufacturing a semiconductor device, according to anembodiment of the present invention, includes a step of forming asemiconductor integrated circuit and an antenna electrically connectedto the semiconductor integrated circuit; a step of sandwiching thesemiconductor integrated circuit and the antenna between a firstinsulator and a second insulator which are provided to face each other;a step of immersing a stack of the semiconductor integrated circuit, theantenna, the first insulator, and the second insulator in a solutionincluding a catalyst material, and making the catalyst material adsorbedon a surface of the stack; and a step of immersing the stack to whichthe catalyst material is adsorbed in a plating solution including aconductive material to form a conductive shield covering the surface ofthe stack to which the catalyst material is adsorbed.

The insulator may be bonded to the semiconductor integrated circuit by abonding layer, in which case, the bonding layer is provided between thesemiconductor integrated circuit and the insulator. In addition, theinsulator and the semiconductor integrated circuit may be directlybonded to each other by heat treatment and pressure treatment.

Note that according to an embodiment of the present invention, asemiconductor device refers to a device which can function by utilizingthe semiconductor characteristics. By using an embodiment of the presentinvention, a semiconductor device having a circuit including asemiconductor element (such as a transistor, a memory element, or adiode), and a semiconductor device such as a chip including a processorcircuit can be manufactured.

With the use of the conductive shield covering a semiconductorintegrated circuit, electrostatic breakdown (malfunctions of the circuitor damages of a semiconductor element) due to electrostatic discharge ofthe semiconductor integrated circuit is prevented. Further, by using apair of insulators between which the semiconductor integrated circuit issandwiched, a highly reliable semiconductor device that is reduced inthickness and size and has tolerance can be provided. In addition,defective shapes and defective characteristics due to the externalstress or an electrostatic discharge are prevented in the manufacturingprocess, so that a semiconductor device can be manufactured with highyield. In addition, a semiconductor device can be formed with highproductivity at low cost because a plating method is used for theformation of the conductive shield.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1E are diagrams illustrating a method for manufacturing asemiconductor device.

FIGS. 2A to 2C are diagrams illustrating semiconductor devices.

FIGS. 3A to 3C are diagrams illustrating semiconductor devices.

FIGS. 4A to 4C are diagrams illustrating a method for manufacturing asemiconductor device.

FIGS. 5A and 5B are diagrams illustrating the method for manufacturingthe semiconductor device.

FIGS. 6A to 6E are diagrams illustrating a method for manufacturing asemiconductor device.

FIGS. 7A to 7C are diagrams illustrating the method for manufacturingthe semiconductor device.

FIGS. 8A and 8B are diagrams illustrating the method for manufacturingthe semiconductor device.

FIGS. 9A to 9G are diagrams illustrating application examples of asemiconductor device.

FIG. 10 is a diagram illustrating a semiconductor device.

FIGS. 11A to 11C are diagrams each illustrating a semiconductor device.

FIG. 12 is a block diagram illustrating a structure of a microprocessorwhich can be obtained using a semiconductor device.

FIG. 13 is a block diagram illustrating a structure of an RFCPU whichcan be obtained using a semiconductor device.

FIGS. 14A and 14B are diagrams each illustrating a semiconductor device.

FIGS. 15A and 15B are diagrams each illustrating a semiconductor device.

FIGS. 16A to 16D are diagrams illustrating a method for manufacturing asemiconductor device.

FIGS. 17A to 17D are diagrams illustrating a method for manufacturing asemiconductor device.

FIGS. 18A to 18D are diagrams illustrating semiconductor devices.

FIG. 19 is a diagram illustrating a semiconductor device.

FIGS. 20A and 20B are diagrams each illustrating a semiconductor device.

FIGS. 21A to 21C are diagrams illustrating a semiconductor device.

FIGS. 22A to 22C are diagrams each illustrating a semiconductor device.

FIGS. 23A1, 23A2, 23B1, and 23B2 are diagrams illustrating a method formanufacturing a semiconductor device.

FIGS. 24A1 and 24A2 are diagrams illustrating the method formanufacturing the semiconductor device.

FIGS. 25A to 25D are diagrams illustrating a method for manufacturing asemiconductor device.

FIGS. 26A to 26D are diagrams illustrating a method for manufacturing asemiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described with reference tothe accompanying drawings. However, the present invention is not limitedto the following description, and it will be easily understood by thoseskilled in the art that various changes and modifications can be made tothe modes and their details without departing from the spirit and scopeof the present invention. Therefore, the present invention should not beconstrued as being limited to the description in the followingembodiments. Note that a common reference numeral refers to the samepart or a part having a similar function throughout the drawings in thestructure of the present invention described below, and the descriptionthereof is omitted.

Embodiment 1

In this embodiment, a highly reliable semiconductor device and a methodfor manufacturing a semiconductor device with high yield will bedescribed in detail with reference to FIGS. 1A to 1E, FIGS. 2A to 2C,and FIGS. 3A to 3C.

In a semiconductor device according to this embodiment, a semiconductorintegrated circuit is separated from a substrate over which thesemiconductor integrated circuit has been formed and is sandwichedbetween flexible insulators. Note that in this specification, thesubstrate over which the semiconductor integrated circuit has beenformed is also referred to as a formation substrate. Thus, thesemiconductor integrated circuit is formed over the formation substratewith a separation layer interposed therebetween.

Semiconductor devices of this embodiment are illustrated in FIGS. 3A,3B, and 3C. In FIG. 3A, an antenna 101 and a semiconductor integratedcircuit 100 that is electrically connected to the antenna 101 aresandwiched between a first insulator 112 and a second insulator 102. Aconductive shield 140 is provided on outer sides of the first insulator112 and the second insulator 102 (on sides where the semiconductorintegrated circuit 100 is not provided) and side surfaces of a stack ofthe antenna 101, the semiconductor integrated circuit 100, the firstinsulator 112 and the second insulator 102. In addition, the antenna 101may be provided below the semiconductor integrated circuit 100 or anouter side of the conductive shield 140 (not to be overlapped with thesemiconductor integrated circuit 100). The conductive shield 140 formedon the outer sides of the first insulator 112 and the second insulator102 is a continuous film to be formed in one process, or the conductiveshield 140 formed on the outer side of the first insulator 112 and theconductive shield 140 formed on the outer side of the second insulator102 are at least electrically connected to each other.

In particular, the conductive shield 140 formed on the outer side of thefirst insulator 112 is electrically connected to the conductive shield140 formed on the outer side of the second insulator 102, so that staticelectricity can be effectively diffused and localization of charge canbe prevented effectively, compared to the case where conductive shieldswhich are not electrically connected to each other are formed on theouter sides of the first insulator 112 and the second insulator 102 orthe case where a conductive shield is provided on one of the firstinsulator 112 and the second insulator 102. As a result, breakdown ofthe semiconductor integrated circuit 100 due to static electricity canbe prevented more effectively.

The conductive shield 140 may be formed by a plating method to cover theentire periphery (a top surface, a bottom surface, and side surfaces) ofthe semiconductor device (to wrap the semiconductor device), or aconductive region that electrically connects the conductive shields 140provided on the outer sides of the first insulator 112 and the secondinsulator 102 may be formed. The conductive region may be part of theside surface of the semiconductor device, or may be an electrode layerthat penetrates inside the semiconductor device. Note that the sidesurface of the semiconductor device refers to a cut surface (dividedsurface) that is generated when a plurality of semiconductor integratedcircuit chips provided on the same insulator is cut (divided) intoindividual chips. The entire cut surface or part of the cut surface maybe covered with the conductive shield 140.

A plan view of the semiconductor device illustrated in FIGS. 3A and 3Bis illustrated in FIG. 3C. In FIG. 3C, a stack 143 including the firstinsulator 112, the antenna 101, the semiconductor integrated circuit100, and the second insulator 102 is covered with a conductive shield140 a (on the first insulator 112 side (also referred to as a frontsurface side or a top surface side)), a conductive shield 140 b (on thesecond insulator 102 side (also referred to as a back surface side or abottom surface side)), and conductive shields 140 c 1, 140 c 2, 140 c 3,and 140 c 4 (on the side surface sides).

FIG. 22A illustrates a structure in which at least one side surface iscovered with the conductive shield 140. FIG. 22B illustrates an examplein which the conductive shields 140 a and 140 b formed on the surfacesare electrically connected to each other by an electrode layer 141 athat penetrates inside the semiconductor device, while FIG. 22Cillustrates an example in which the conductive shields 140 a and 140 bformed on the surfaces are electrically connected to each other by theelectrode layer 141 a and an electrode layer 141 b. The electrode layers141 a and 141 b can be formed by forming through-holes before theconductive shields are formed by a plating method and by filling thethrough-holes with a plating solution. Note that FIGS. 22B and 22Cillustrate examples in which the individual antenna 101 and theindividual semiconductor integrated circuit 100 are divided before theantenna 101 and the semiconductor integrated circuit 100 are bonded tothe second insulator 102, and the second insulator 102 is bonded to soas to fill an opening. Therefore, in the cross-sectional view of FIGS.22B and 22C, the antenna 101 and the semiconductor integrated circuit100 are divided by the insulator.

The conductive shield 140 is provided on the entire surface of a regionthat overlaps the semiconductor integrated circuit 100 so as to coverthe semiconductor integrated circuit 100, and the semiconductorintegrated circuit 100 is sandwiched.

The conductive shield 140 is not electrically connected to thesemiconductor integrated circuit 100 and the antenna 101.

A semiconductor device of this embodiment is a wireless signalprocessing unit having a function of sending and receiving signalsto/from an external device by wireless communication. Accordingly, theconductive shield 140 transmits an electromagnetic wave that the antenna101 included in the semiconductor device should send and receive, andexternal static electricity is prevented from being applied to thesemiconductor integrated circuit 100 in the semiconductor device. Theconductive shield 140 diffuses static electricity applied byelectrostatic discharge to dissipate it or prevents local electriccharges (localization of electric charges) (prevents local potentialdifference) so that electrostatic breakdown of the semiconductorintegrated circuit 100 can be prevented.

The conductive shields that are electrically connected to each other areprovided on both a front surface and a back surface of the semiconductorintegrated circuit 100; therefore, a wide region of the semiconductorintegrated circuit 100 is protected from external static electricity,and a higher effect of prevention of electrostatic breakdown can beobtained.

One surface of the semiconductor integrated circuit 100, on which theantenna 101 is not provided, has weak tolerance to electrostaticdischarge (ESD); therefore, the conductive shield 140 on the secondinsulator 102 side may have a larger thickness than the conductiveshield 140 on the first insulator 112 side.

The semiconductor device described in this embodiment performs operation(has a radio transmission function) by generating induced electromotiveforce due to an external electromagnetic wave. Therefore, the conductiveshield needs to prevent breakdown of the semiconductor integratedcircuit due to static electricity and to be formed using a conductivematerial that transmits the electromagnetic wave.

In general, it is known that the electromagnetic wave is attenuated in asubstance, and this attenuation is remarkable in the conductivematerial, particularly. Therefore, the conductive shield has asufficiently small thickness so that the electromagnetic wave can betransmitted through the conductive shield in this embodiment.

The thickness of the conductive shield may be set considering afrequency of an electromagnetic wave used for communication, orresistance and magnetic permeability of the conductive material used forthe conductive shield.

For example, when a conductive material having resistivity ρ of 5.5×10⁻⁷(Ω·m) is used as the conductive shield and a frequency of anelectromagnetic wave is 13.56 MHz, the conductive shield has a thicknessof at most less than or equal to about 500 nm. Thus, breakdown of thesemiconductor device resulting from electrostatic discharge issuppressed, and communication with the outside can be performedfavorably.

When a conductive material having higher resistivity is used, theconductive shield may be formed to have a thickness of less than orequal to about 700 nm.

It is preferable that the lower limit of the thickness of the conductiveshield be determined based on resistivity. For example, when aconductive material to be used for the conductive shield has a highresistivity, it is preferable that the conductive shield be formed tohave a large thickness in order to diffuse static electricityeffectively. When a thin conductive shield is formed using a conductivematerial having a high resistivity, sheet resistance increases, andstatic electricity cannot be diffused effectively in the case whereelectrostatic discharge is generated; therefore, large current mightflow to the semiconductor integrated circuit and the semiconductorintegrated circuit might be broken down.

Therefore, in order to effectively prevent breakdown of thesemiconductor device due to static electricity, it is preferable thatthickness be set so that the sheet resistance of the conductive shieldis less than or equal to 1.0×10⁷ Ω/square, more preferably, less than orequal to 1.0×10⁴ Ω/square, further preferably, less than or equal to1.0×10² Ω/square.

Note that if the sheet resistance of the conductive shield is within theabove range, it is preferable that the thickness of the conductiveshield be as small as possible in terms of transmitting theelectromagnetic wave.

Note that when a material having a low resistivity is used as theconductive material, the sheet resistance can be reduced sufficientlyand the electromagnetic wave can be easily transmitted even in the casewhere the thickness of the conductive shield is extremely small;however, the thickness may be greater than or equal to about 1 nm (morepreferably, greater than or equal to 3 nm) in consideration of amanufacture process or the like.

On the other hand, it is preferable that the thickness be at leastgreater than or equal to 5 nm when a material having a relatively highresistivity is used.

Such a conductive shield is formed, whereby breakdown of thesemiconductor device due to an electrostatic discharge can beeffectively suppressed, and the semiconductor device by whichcommunication with the outside can be performed favorably can beobtained.

Next, materials or the like which can be applied to the structureillustrated in FIGS. 1A to 1E will be described in detail.

The conductive shield may have conductivity, and a conductive layerformed using a conductive material can be used. In an embodiment of thepresent invention, the conductive layer which is used for the conductiveshield is formed using a film including metal by a plating method.

In an embodiment of the present invention, a wet plating method by whicha film including metal is formed by reducing metal ions that exist in anaqueous solution by electrons is used. When the wet plating method isclassified in terms of a reduction method, there are a reduction methodby electricity (electrolytic (electric) plating method), a reductionmethod by a reducing agent (electroless plating method), a reductionmethod by a difference of an ionization tendency (displacement platingmethod), and the like. In an embodiment of the present invention, theaforementioned wet plating method can be used, and a combination of theaforementioned wet plating methods may be used.

A film can be formed isotropically with respect to an object by a wetplating method; therefore, a region where the film can be formed islarge, and a conductive shield that covers a periphery (a top surface, abottom surface, and side surfaces) of a semiconductor device can beformed in one plating process. The conductive shield formed in oneplating process can be a continuous film.

By a plating method, a region that can be treated at a time can belarge, productivity can be improved, and cost for a process can bereduced to achieve low cost. Therefore, when a conductive shield isformed by using a plating method, a semiconductor device of anembodiment of the present invention can be formed with high productivityat low cost. Lower cost of a process allows a semiconductor device to beprovided at lower cost.

Such a conductive shield 140 is formed using a material to a thicknessto transmit the electromagnetic wave that should be sent and received bythe sandwiched antenna and semiconductor integrated circuit and toprevent static electricity. Thus, a semiconductor device which hastolerance to electrostatic breakdown and has high reliability and whichcan send and receive data by wireless communication through the antennacan be provided.

As the conductive shield 140, a single layer or a stacked layer of afilm including metal which can be formed by a wet plating method can beused.

The conductive shield 140 may be formed using an element selected fromnickel, copper, tin, silver, gold, platinum, palladium, zinc, cadmium,chromium, iron, cobalt, and tungsten; or an alloy material containingthe element as its main component, for example.

As an alloy material, a nickel alloy (a nickel phosphorus (NiP) alloy, anickel boron (NiB) alloy, a nickel cobalt (NiCo) alloy, a nickel cobaltphosphorus (NiCoP) alloy, a nickel iron phosphorus (NiFeP) alloy, anickel tungsten phosphorus (NiWP) alloy, and the like), a zinc alloy (azinc iron alloy, a zinc nickel alloy, and a tin zinc alloy), a tin alloy(a tin silver alloy, a tin cobalt alloy), a copper zinc alloy (brass),and the like can be given.

A film including metal formed by a plating method, a film of metal,metal nitride, metal oxide, or the like formed by another manufacturingmethod (various dry methods such as a sputtering method, a plasma CVDmethod, or an evaporation method; a coating method; a printing method; adroplet discharge method (an ink-jet method); or the like), or a stackedlayer of those films may be used. The metal nitride or the metal oxidecan also be formed by nitriding or oxidizing the surface of the metalfilm.

For the metal nitride, tantalum nitride, titanium nitride, or the likecan be used.

As the metal oxide, indium tin oxide (ITO), indium tin oxide containingsilicon oxide (ITSO), organoindium, organotin, zinc oxide, or the likecan be used. Alternatively, indium zinc oxide (IZO) containing zincoxide (ZnO), zinc oxide (ZnO), ZnO containing gallium (Ga), tin oxide(SnO₂), indium oxide containing tungsten oxide, indium zinc oxidecontaining tungsten oxide, indium oxide containing titanium oxide,indium tin oxide containing titanium oxide, or the like may also beused.

Note that depending on a wet plating method and a conductive material tobe used, formation of a conductive film (a seed layer), adsorption of acatalytic material, or the like in a region (a body to be plated) wherea plating film is formed is performed as appropriate.

In addition, a protective layer may be stacked over the conductiveshield 140. As the protective layer, a nitride material (e.g., tantalumnitride, titanium nitride, or the like) or an oxide material (e.g.,titanium oxide or the like) can be used. Even when the conductive shield140 is provided on the surface of the semiconductor device, theprotective layer serves as an outermost surface; therefore,deterioration of the conductive shield 140 can be prevented. Theprotective layer may have a thickness of greater than or equal to about10 nm and less than or equal to about 200 nm.

For the insulator, a structure body in which a fibrous body isimpregnated with an organic resin can be used. In FIGS. 2A to 2C,examples are illustrated in which a structure body in which a fibrousbody is impregnated with an organic resin is used for each of the firstinsulator 112 and the second insulator 102. FIGS. 2A and 2B correspondto FIGS. 3A and 3B, respectively.

The structure body in which a fibrous body is impregnated with anorganic resin is used for each of the first insulator 112 and the secondinsulator 102. A structure body in which a fibrous body 160 isimpregnated with an organic resin 161 is used for the first insulator112, and a structure body in which a fibrous body 150 is impregnatedwith an organic resin 151 is used for the second insulator 102.

FIG. 2C is a plan view of the fibrous body 160 which is a woven fabricformed using yarn bundles of fibers for the warp yarn and the weft yarn.

As illustrated in FIG. 2C, the fibrous body 160 is woven using warpyarns spaced at regular intervals and weft yarns spaced at regularintervals. Such a fibrous body that is woven using the warp yarns andthe weft yarns has regions without the warp yarns and the weft yarns. Inthe fibrous body 160, the fibrous body is more easily impregnated withthe organic resin 161, whereby adhesiveness between the fibrous body 160and the semiconductor integrated circuit can be increased.

In addition, in the fibrous body 160, density of the warp yarns and theweft yarns may be high and a proportion of the regions without the warpyarns and the weft yarns may be low.

The structure body in which the fibrous body 160 is impregnated with theorganic resin 161 is also referred to as a prepreg. A prepreg is formedspecifically as follows: after a fibrous body is impregnated with avarnish in which a matrix resin is diluted with an organic solvent,drying is performed so that the organic solvent is volatilized and thematrix resin is semi-cured. The thickness of the structure body ispreferably greater than or equal to 10 μm and less than or equal to 100μm, more preferably, greater than or equal to 10 μm and less than orequal to 30 μm. With the use of the structure body with such athickness, a semiconductor device which is thin and can be bent can bemanufactured. For example, a prepreg having a modulus of elasticity ofgreater than or equal to 13 GPa and less than or equal to 15 GPa and amodulus of rupture of 140 MPa can be used for the insulator.

Note that the structure body in which a fibrous body is impregnated withan organic resin may have a stacked structure. In that case, thestructure body may be a stack of a plurality of structure bodies in eachof which a single-layer fibrous body is impregnated with an organicresin or may be a structure body in which a plurality of fibrous bodiesstacked is impregnated with an organic resin. Further, in stacking aplurality of structure bodies in each of which a single-layer fibrousbody is impregnated with an organic resin, another layer may besandwiched between the structure bodies.

A thermosetting resin such as an epoxy resin, an unsaturated polyesterresin, a polyimide resin, a bismaleimide-triazine resin, or a cyanateresin can be used as the organic resin 161. Alternatively, athermoplastic resin such as a polyphenylene oxide resin, apolyetherimide resin, or a fluorine resin can be used as the organicresin 161. Still alternatively, a plurality of resins selected from theabove thermosetting resins and thermoplastic resins may be used as theorganic resin 161. By using the above organic resin, the fibrous bodycan be bonded to the semiconductor integrated circuit by heat treatment.The higher the glass transition temperature of the organic resin 161 is,the less easily the organic resin 161 is damaged by local pressure,which is preferable.

Highly thermally-conductive filler may be dispersed in the organic resin161 or the yarn bundles of fibers. As the highly thermally-conductivefiller, aluminum nitride, boron nitride, silicon nitride, alumina, andthe like can be given. As the highly thermally-conductive filler, ametal particle such as silver or copper can also be given. When theconductive filler is included in the organic resin or the yarn bundlesof fibers, heat generated in the semiconductor integrated circuit can beeasily released to the outside. Accordingly, thermal storage in thesemiconductor device can be suppressed and thus the semiconductor devicecan be prevented from being damaged.

The fibrous body 160 is a woven or nonwoven fabric using high-strengthfibers of an organic compound or an inorganic compound, and a pluralityof fibrous bodies is provided so as to partly overlap with each other.The high-strength fiber is specifically a fiber with a high modulus ofelasticity in tension or a fiber with a high Young's modulus. As typicalexamples of the high-strength fiber, a polyvinyl alcohol fiber, apolyester fiber, a polyamide fiber, a polyethylene fiber, an aramidfiber, a polyparaphenylenebenzobisoxazole fiber, a glass fiber, a carbonfiber, and the like can be given. As a glass fiber, a glass fiber usingE glass, S glass, D glass, Q glass, or the like can be given. Note thatthe fibrous body 160 may be formed from one kind of the abovehigh-strength fibers or a plurality of the above high-strength fibers.

The fibrous body 160 may be a woven fabric which is woven using bundlesof fibers (single yarns) (hereinafter, the bundles of fibers arereferred to as yarn bundles) for warp yarns and weft yarns, or anonwoven fabric obtained by stacking yarn bundles of plural kinds offibers randomly or in one direction. In the case of a woven fabric, aplain-woven fabric, a twilled fabric, a satin-woven fabric, or the likecan be used as appropriate.

The yarn bundle may have a circular shape or an elliptical shape incross section. As the yarn bundle of fibers, a yarn bundle of fiberswhich has been subjected to fiber opening with a high-pressure waterstream, high-frequency vibration using liquid as a medium, continuousultrasonic vibration, pressing with a roller, or the like may be used. Ayarn bundle of fibers which is subjected to fabric opening has a largewidth, has a smaller number of single yarns in the thickness direction,and has an elliptical shape or a flat shape in cross section. Further,by using a loosely twisted yarn for the yarn bundle of fibers, the yarnbundle is easily flattened and has an elliptical shape or a flat shapein cross section. Using a yarn bundle having an elliptical shape or aflat shape in cross section in this manner can reduce the thickness ofthe fibrous body 160. Accordingly, the thickness of the fibrous body 160can be reduced, and thus a thin semiconductor device can bemanufactured.

Note that in drawings of this embodiment, the fibrous body 160 isillustrated as a woven fabric which is plain-woven using a yarn bundlehaving an elliptical shape in cross section.

Further, in order to enhance permeability of an organic resin into theinside of the yarn bundle of fibers, the fiber may be subjected tosurface treatment. For example, as the surface treatment, coronadischarge treatment, plasma discharge treatment, and the like foractivating a surface of the fiber can be given. Further, surfacetreatment using a silane coupling agent or a titanate coupling agent canbe given.

In addition, a material having low modulus of elasticity and highbreaking strength may be used as the first insulator 112 and the secondinsulator 102. For example, as the first insulator 112 and the secondinsulator 102, a rubber elastic film having a modulus of elasticity ofgreater than or equal to 5 GPa and less than or equal to 12 GPa and amodulus of rupture of greater than or equal to 300 MPa can be used.

The first insulator 112 and the second insulator 102 are each preferablyformed using a high-strength material. As typical examples of thehigh-strength material, a polyvinyl alcohol resin, a polyester resin, apolyamide resin, a polyethylene resin, an aramid resin, apolyparaphenylenebenzobisoxazole resin, a glass resin, and the like canbe given. When the first insulator 112 and the second insulator 102 eachformed using a high-strength material having elasticity are provided,load such as local pressure is diffused and absorbed through the entirelayer; therefore, the semiconductor device can be prevented from beingdamaged.

More specifically, as the first insulator 112 and the second insulator102, an aramid resin, a polyethylene naphthalate (PEN) resin, apolyethersulfone (PES) resin, a polyphenylene sulfide (PPS) resin, apolyimide (PI) resin, or the like can be used.

The semiconductor integrated circuit 100 or the antenna 101 may bebonded to the first insulator 112 or the second insulator 102 by using abonding layer. The bonding layer may be able to bond the insulators andthe semiconductor integrated circuit, and a thermosetting resin, anultraviolet curable resin, an acrylic resin, a urethane resin, an epoxyresin, a silicone resin, or the like can be used. The bonding layer mayhave a thickness of greater than or equal to about 3 μm and less than orequal to about 15 μm. When the semiconductor integrated circuit 100 isbonded to the first insulator 112 and the second insulator 102 by heattreatment and pressure treatment, the bonding layer is not necessarilyused.

In addition, a protective layer may be formed over the semiconductorintegrated circuit. Examples are illustrated in FIG. 3B and FIG. 2B ineach of which an inorganic insulating layer 105 is formed as aprotective layer over the semiconductor integrated circuit 100. Further,FIG. 3B and FIG. 2B each illustrate an example in which the antenna 101is formed over the semiconductor integrated circuit 100 and theinorganic insulating layer 105 is formed over the antenna 101. Theinorganic insulating layer 105 covers the antenna 101, therebypreventing oxidation or the like of a conductive layer functioning as anantenna.

The inorganic insulating layer 105 is formed to have a single-layerstructure or a stacked structure using an inorganic compound by asputtering method, a plasma CVD method, a coating method, a printingmethod, or the like. As typical examples of the inorganic compound,oxide of silicon and nitride of silicon can be given. As typicalexamples of the oxide of silicon and the nitride of silicon, siliconoxide, silicon oxynitride, silicon nitride, silicon nitride oxide, andthe like can be given. Note that a silicon oxynitride film in thisspecification means a film that contains more oxygen than nitrogen andincludes oxygen, nitrogen, silicon, and hydrogen at concentrationsranging from 55 at. % to 65 at. %, 1 at. % to 20 at. %, 25 at. % to 35at. %, and 0.1 at. % to 10 at. %, respectively. Further, a siliconnitride oxide film means a film that contains more nitrogen than oxygenand includes oxygen, nitrogen, silicon, and hydrogen at concentrationsranging from 15 at. % to 30 at. %, 20 at. % to 35 at. %, 25 at. % to 35at. %, and 15 at. % to 25 at. %, respectively.

Moreover, the inorganic insulating layer 105 may have a stackedstructure. For example, inorganic compounds may be stacked to form theinorganic insulating layer 105. Typically, two or more of silicon oxide,silicon nitride oxide, and silicon oxynitride may be stacked to form theinorganic insulating layer 105.

A method for manufacturing a semiconductor device of an embodiment ofthe present invention will be described with reference to FIGS. 1A to1E. The antenna 101 and the semiconductor integrated circuit 100 areformed over a substrate 110 having an insulating surface which is aformation substrate with a separation layer 111 interposed between thesemiconductor integrated circuit 100 and the substrate 110 (see FIG.1A).

As the substrate 110, which is a formation substrate, a glass substrate,a quartz substrate, a sapphire substrate, a ceramic substrate, a metalsubstrate having an insulating layer on a surface thereof, or the likecan be used. Alternatively, a plastic substrate which can withstand theprocess temperature of this embodiment may be used. In the manufacturingprocess of a semiconductor device, a formation substrate can be selectedas appropriate in accordance with the process.

The separation layer 111 is formed to have a single-layer structure or astacked structure including a layer formed of an element selected fromtungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium(Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium(Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), andsilicon (Si); or an alloy or compound material containing any of theelements as its main component by a sputtering method, a plasma CVDmethod, a coating method, a printing method, or the like. A layercontaining silicon may have an amorphous structure, a microcrystallinestructure, or a polycrystalline structure. Note that a coating methodincludes a spin-coating method, a droplet discharge method, and adispensing method in its category here.

When the separation layer 111 has a single-layer structure, a tungstenlayer, a molybdenum layer, or a layer containing a mixture of tungstenand molybdenum is preferably formed. Alternatively, a layer containingoxide or oxynitride of tungsten, a layer containing oxide or oxynitrideof molybdenum, or a layer containing oxide or oxynitride of a mixture oftungsten and molybdenum is formed. Note that the mixture of tungsten andmolybdenum corresponds, for example, to an alloy of tungsten andmolybdenum.

When the separation layer 111 has a stacked structure, it is preferableto form, as a first layer, a tungsten layer, a molybdenum layer, or alayer containing a mixture of tungsten and molybdenum, and form, as asecond layer, oxide, nitride, oxynitride, or nitride oxide of tungsten,molybdenum, or a mixture of tungsten and molybdenum.

When the separation layer 111 has a stacked structure of a layercontaining tungsten and a layer containing tungsten oxide, the layercontaining tungsten may be formed first and an insulating layer formedof oxide may be formed on the layer containing tungsten so that a layercontaining tungsten oxide can be formed at the interface between thetungsten layer and the insulating layer. Further, the surface of thelayer containing tungsten may be subjected to thermal oxidationtreatment, oxygen plasma treatment, or treatment using a strongoxidizing solution such as ozone water to form a layer containing oxideof tungsten. In addition, plasma treatment or heat treatment may beperformed in an atmosphere of oxygen, nitrogen, or dinitrogen monoxide,or a mixed gas of the gas and another gas. The same applies to the caseof forming a layer containing nitride, oxynitride, or nitride oxide oftungsten. After a layer containing tungsten is formed, a silicon nitridelayer, a silicon oxynitride layer, or a silicon nitride oxide layer maybe formed thereover.

Although the separation layer 111 is formed to be in contact with thesubstrate 110 according to the above process, an embodiment of thepresent invention is not limited to this process. An insulating layer tobe a base may be formed in contact with the substrate 110, and theseparation layer 111 may be provided in contact with the insulatinglayer.

The semiconductor integrated circuit 100 and the first insulator 112 arebonded to each other, and the semiconductor integrated circuit 100 isseparated from the substrate 110 using the separation layer 111.Accordingly, the semiconductor integrated circuit 100 is provided on thefirst insulator 112 side (see FIG. 1B).

In this embodiment, the structure body in which the fibrous body 160 isimpregnated with the organic resin 161 is used for the first insulator112. The structure body is heated and subjected to pressure bonding, sothat the organic resin of the structure body is plasticized or cured.Note that when the organic resin is an organic plastic resin, theorganic resin which is plasticized is then cured by cooling the organicresin to room temperature. By heating and pressure bonding, the organicresin is uniformly spread so as to be in close contact with thesemiconductor integrated circuit, and is cured. The step in which thestructure body is subjected to pressure bonding is performed under anatmospheric pressure or a reduced pressure.

Any of the following methods can be appropriately used as a step fortransferring the semiconductor integrated circuit to another substrate:a method in which a separation layer is formed between a substrate and asemiconductor integrated circuit, a metal oxide film is formed betweenthe separation layer and the semiconductor integrated circuit, the metaloxide film is weakened by crystallization, and the semiconductorintegrated circuit is separated; a method in which an amorphous siliconfilm containing hydrogen is provided between a substrate having highheat resistance and a semiconductor integrated circuit, and theamorphous silicon film is irradiated with a laser beam or etched toremove the amorphous silicon film, thereby separating the semiconductorintegrated circuit; a method in which a separation layer is formedbetween a substrate and a semiconductor integrated circuit, a metaloxide film is provided between the separation layer and thesemiconductor integrated circuit, the metal oxide film is weakened bycrystallization, part of the separation layer is etched away using asolution or a halogen fluoride gas such as NF₃, BrF₃, or ClF₃, andseparation is performed at the weakened metal oxide film; a method inwhich a substrate over which a semiconductor integrated circuit isformed is mechanically removed or is etched away using a solution or ahalogen fluoride gas such as NF₃, BrF₃, or ClF₃; or the like.Alternatively, it is also possible to use a method in which a filmcontaining nitrogen, oxygen, hydrogen, or the like (e.g., an amorphoussilicon film containing hydrogen, an alloy film containing hydrogen, oran alloy film containing oxygen) is used as a separation layer, and theseparation layer is irradiated with a laser beam so that nitrogen,oxygen, or hydrogen contained in the separation layer is discharged as agas, whereby separation of the semiconductor integrated circuit from thesubstrate is facilitated may be used.

By combining any of the above separation methods, the transferring stepcan be more easily performed. That is, the separation can also beperformed with physical force (by a machine or the like) afterperforming laser irradiation; etching to the separation layer with agas, a solution, or the like; or mechanical removal with a sharp knife,scalpel, or the like; so as to make a condition where the separationlayer and the semiconductor integrated circuit can be easily separatedfrom each other.

Alternatively, a liquid may be made to permeate an interface between theseparation layer and the semiconductor integrated circuit, and then thesemiconductor integrated circuit is separated from the formationsubstrate.

Similarly to the first insulator 112, the second insulator 102 is formedusing the structure body in which the fibrous body 150 is impregnatedwith the organic resin 151.

The structure body is heated and subjected to pressure bonding, and thesecond insulator 102 is bonded to a separation surface where thesemiconductor integrated circuit 100 is exposed, whereby the antenna 101and the semiconductor integrated circuit 100 are sandwiched between thefirst insulator 112 and the second insulator 102 (see FIG. 1C).

Although not illustrated, a plurality of semiconductor integratedcircuits is sandwiched between the first insulator 112 and the secondinsulator 102, and then the semiconductor integrated circuits 100 areindividually divided, whereby the stacks 143 which are semiconductorintegrated circuit chips are formed. There is no particular limitationon a separation means as long as physical separation is possible, andseparation is performed by laser beam irradiation in this embodiment.

By separation, the antenna 101 and the semiconductor integrated circuit100 are sealed by the first insulator 112 and the second insulator 102,and divided surfaces (side surfaces generated by separation) are formedon the chips.

The stack 143 is immersed in a plating solution 145 including a platingmetal material, and a film including metal is grown on the stack 143(see FIG. 1D). The immersion time is controlled so as to obtain adesired film thickness and the conductive shield 140 is formed (see FIG.1E).

Accordingly, the antenna 101 and the semiconductor integrated circuit100 are sealed by the first insulator 112 and the second insulator 102and protected against electrostatic discharge using the conductiveshield 140 that is provided on outer sides of the first insulator 112and the second insulator 102 which correspond to the surface and backsurface of the semiconductor device and on side surfaces of the stack.

The plating solution 145 may be in contact with a region to be plated ofthe stack 143; therefore, an immersion method is not limited. Therefore,the stack 143 may be placed obliquely (or perpendicularly) and theplating solution 145 may be applied to the stack 143 in such a way thatthe plating solution 145 flows on the surface of the stack 143. When theplating is performed so that the solution is applied to the stack 143placed obliquely (or perpendicularly), there is an advantage ofdownsizing an apparatus which is used for the process of a largesubstrate.

With the use of the conductive shield covering a semiconductorintegrated circuit, electrostatic breakdown (malfunctions of the circuitor damages of a semiconductor element) due to electrostatic discharge ofthe semiconductor integrated circuit is prevented. Further, by using apair of insulators between which the semiconductor integrated circuit issandwiched, a highly reliable semiconductor device that is reduced inthickness and size and has tolerance can be provided. In addition,defective shapes and defective characteristics due to the externalstress or an electrostatic discharge are prevented in the manufacturingprocess, so that a semiconductor device can be manufactured with highyield. In addition, a semiconductor device can be formed with highproductivity at low cost because a plating method is used for theformation of the conductive shield.

Embodiment 2

In this embodiment, another example of a semiconductor device forproviding high reliability and a method for manufacturing thesemiconductor device with the use of an embodiment of the presentinvention will be described with reference to FIGS. 14A and 14B, FIGS.15A and 15B, FIGS. 16A to 16D, and FIGS. 17A to 17D. In the structure ofthis embodiment described below, a common reference numeral refers tothe same part or a part having a similar function throughout drawings,in Embodiment 1 and this embodiment, and the description thereof isomitted.

An example in which an insulator has a stacked structure is described inthis embodiment. In FIG. 14A, the antenna 101 and the semiconductorintegrated circuit 100 that is connected to the antenna 101 aresandwiched between the first insulator 112 and the second insulator 102.A third insulator 103 is provided between the semiconductor integratedcircuit 100 and the second insulator 102, and the conductive shield 140is provided on the outer sides of the first insulator 112 and the secondinsulator 102 (on the sides where the semiconductor integrated circuit100 is not provided) and side surfaces of a semiconductor device. Theconductive shield 140 may be formed on all the side surfaces to surround(wrap) the periphery of the semiconductor device or may be formed tocover part of the side surfaces of the semiconductor device. Theconductive shield formed on the outer side of the first insulator 112 iselectrically connected to the conductive shield formed on the outer sideof the second insulator 102 in an embodiment of the present invention.In this embodiment, the conductive shield 140 is formed in the sameplating process on the outer sides of the first insulator 112 and thesecond insulator 102, and is a continuous film.

FIG. 14B is an example in which the semiconductor integrated circuit 100and the third insulator 103 are bonded to each other using a bondinglayer 104. An acrylic resin is used for the bonding layer 104 in FIG.14B.

It is preferable that the third insulator 103 provided between thesemiconductor integrated circuit 100 and the second insulator 102 havelower modulus of elasticity and higher breaking strength than the firstinsulator 112 and the second insulator 102 so that the third insulator103 can function as an impact diffusion layer.

The third insulator 103 is provided to be in contact with and near thesemiconductor integrated circuit, which has an effect of diffusing andreducing force that is applied to the semiconductor integrated circuitfrom the outside.

For the first insulator 112 and the second insulator 102 in FIGS. 14Aand 14B, a structure body in which a fibrous body is impregnated with anorganic resin can be used. It is preferable that the first insulator 112and the second insulator 102 in FIGS. 14A and 14B have a modulus ofelasticity of greater than or equal to 13 GPa and a modulus of ruptureof less than 300 MPa.

It is preferable that a material having low modulus of elasticity andhigh breaking strength be used for the third insulator 103. For example,a rubber elastic film having a modulus of elasticity of greater than orequal to 5 GPa and less than or equal to 12 GPa and a modulus of ruptureof greater than or equal to 300 MPa can be used for the third insulator103.

The third insulator 103 is preferably formed using a high-strengthmaterial. As typical examples of the high-strength material, a polyvinylalcohol resin, a polyester resin, a polyamide resin, a polyethyleneresin, an aramid resin, a polyparaphenylenebenzobisoxazole resin, aglass resin, and the like can be given. When the third insulator 103formed using a high-strength material having elasticity is provided,load such as local pressure is diffused and absorbed through the entirelayer; therefore, the semiconductor device can be prevented from beingdamaged.

More specifically, as the third insulator 103, an aramid resin, apolyethylene naphthalate (PEN) resin, a polyethersulfone (PES) resin, apolyphenylene sulfide (PPS) resin, a polyimide (PI) resin, or the likecan be used. In this embodiment, an aramid resin film (modulus ofelasticity of 10 GPa, and breaking strength of 480 MPa) is used as thethird insulator 103.

In addition, a fourth insulator 113 that is similar to the thirdinsulator 103 may be provided on an outer side of the first insulator112 (on the side where the antenna 101 is not provided), as illustratedin FIGS. 15A and 15B.

FIG. 15A is an example in which the fourth insulator 113 that is similarto the third insulator 103 is fixed on an outer side of the firstinsulator 112 by using a bonding layer 114. In this embodiment,an aramidfilm is used for the fourth insulator 113, and an acrylic resin is usedfor the bonding layer 114. When the first insulator 112 and the fourthinsulator 113 are bonded to each other by heat treatment and pressuretreatment, the bonding layer 114 is not necessarily used. In this case,the antenna 101, the first insulator 112, and the fourth insulator 113are directly bonded, as in FIG. 15B. A process of bonding the antenna101 to the first insulator 112, and a process of bonding the firstinsulator 112 to the fourth insulator 113 may be performed at the sametime or may be performed separately.

A method for manufacturing a semiconductor device of an embodiment ofthe present invention will be described with reference to FIGS. 16A to16D. The antenna 101 and the semiconductor integrated circuit 100 areformed over the substrate 110 having an insulating surface which is aformation substrate with the separation layer 111 interposed between thesemiconductor integrated circuit 100 and the substrate 110 (see FIG.16A).

The antenna 101 and the semiconductor integrated circuit 100 are bondedto the first insulator 112, and the semiconductor integrated circuit 100is separated from the substrate 110 by using the separation layer 111.Accordingly, the semiconductor integrated circuit 100 is provided on thefirst insulator 112 side (see FIG. 16B).

Also in FIGS. 16A to 16D, the structure body in which the fibrous body160 is impregnated with the organic resin 161 is used for the firstinsulator 112. The structure body is heated and subjected to pressurebonding, so that the organic resin of the structure body is plasticizedor cured.

Similarly to the first insulator 112, the structure body in which thefibrous body 150 is impregnated with the organic resin 151 is used forthe second insulator 102. The structure body is heated and subjected topressure bonding, so that the third insulator 103 and the secondinsulator 102 are bonded to each other. The bonding layer 104 isprovided on one surface of the third insulator 103, on which the secondinsulator 102 is not provided.

The bonding layer 104 is bonded to the separation surface where thesemiconductor integrated circuit 100 is exposed (see FIG. 16C).

Next, the conductive shield 140 is formed by a wet plating method on thesurfaces of the first insulator 112 and the second insulator 102 andside surfaces of a chip that is cut (see FIG. 16D). In this embodiment,a nickel phosphorus (NiP) alloy film is formed by an electroless platingmethod for the conductive shield 140.

Further, as in FIG. 17D, a structure may be used in which the firstinsulator 112 and the second insulator 102 each with the use of aprepreg are bonded to the semiconductor integrated circuit 100 and theantenna 101, the fourth insulator 113 and the third insulator 103 areprovided on the outer sides of the first insulator 112 and the secondinsulator 102 (on sides where the semiconductor integrated circuit 100or the antenna 101 is not provided), and surfaces of the fourthinsulator 113 and the third insulator 103 and side surfaces of a stackare covered with the conductive shield 140.

As a manufacturing process of a structure illustrated in FIG. 17D, theantenna 101 and the semiconductor integrated circuit 100 are formed overthe substrate 110 having an insulating surface which is a formationsubstrate with the separation layer 111 interposed between thesemiconductor integrated circuit 100 and the substrate 110 (see FIG.17A).

Next, the fourth insulator 113, the first insulator 112, the antenna101, and the semiconductor integrated circuit 100 are heated andsubjected to pressure bonding, and the antenna 101 and the semiconductorintegrated circuit 100 are separated from the substrate 110 using theseparation layer 111 (see FIG. 17B).

The third insulator 103 and the second insulator 102 are heated andsubjected to pressure bonding to the semiconductor integrated circuit100, whereby the third insulator 103 and the second insulator 102 arebonded to the semiconductor integrated circuit 100 (see FIG. 17C).

The conductive shield 140 is formed by a wet plating method so as tocover the stack in which the fourth insulator 113, the first insulator112, the antenna 101, the semiconductor integrated circuit 100, thesecond insulator 102, and the third insulator 103 are stacked (see FIG.17D).

The third insulator 103 and the fourth insulator 113 have an effect ofenhancing strength of the semiconductor device against external stress.In particular, in the case where an insulator like the third insulator103 is provided between the semiconductor integrated circuit 100 and thesecond insulator 102, even when pressure treatment is performed in amanufacturing process, the third insulator 103 diffuses force;therefore, an adverse effect such as damage or deterioration ofcharacteristics is not given to the semiconductor integrated circuit100. Accordingly, a semiconductor device can be formed with high yield.

The conductive shield 140 transmits an electromagnetic wave that theantenna 101 included in the semiconductor device should send andreceive, and external static electricity is prevented from being appliedto the semiconductor integrated circuit 100 in the semiconductor device.The conductive shield 140 diffuses static electricity applied byelectrostatic discharge to dissipate it or prevents local electriccharges (localization of electric charges) (prevents local potentialdifference) so that electrostatic breakdown of the semiconductorintegrated circuit 100 can be prevented.

In addition, the first insulator 112 and the second insulator 102 areprovided against force applied to the semiconductor device from theoutside, and the fourth insulator 113 and the third insulator 103 whichdiffuse the force are provided, whereby locally applied force can bereduced; therefore, damage or deterioration of characteristics of thesemiconductor device can be prevented.

In the structure of FIG. 15A of this embodiment, the insulator is formedusing four layers of the first insulator 112 and the second insulator102 which mainly function as impact resistance layers and which arestructure bodies in each of which a fibrous body is impregnated with anorganic resin and the third insulator 103 and the fourth insulator 113which mainly function as impact diffusion layers and which has a lowmodule of elasticity and high breaking strength. However, at least twolayers of insulators with which the antenna 101 and the semiconductorintegrated circuit 100 are sandwiched may be provided. Accordingly, astructure in which three layers or two layers of the above four layersare used may be used. At least the semiconductor integrated circuit 100and the antenna 101 may be covered with the conductive shield 140 thatis electrically connected to each other, with insulators interposedbetween the semiconductor integrated circuit 100 and the conductiveshield 140 and between the antenna 101 and the conductive shield 140,and then an insulator may be stacked on the conductive shield 140. Whenthe surface of the conductive shield is not exposed, there is an effectof preventing deterioration of the conductive shield such as oxidation,abrasion, or crazing.

With the use of the conductive shield covering a semiconductorintegrated circuit, electrostatic breakdown (malfunctions of the circuitor damages of a semiconductor element) due to electrostatic discharge ofthe semiconductor integrated circuit is prevented. Further, by using apair of insulators between which the semiconductor integrated circuit issandwiched, a highly reliable semiconductor device that is reduced inthickness and size and has tolerance can be provided. In addition,defective shapes and defective characteristics due to the externalstress or an electrostatic discharge are prevented in the manufacturingprocess, so that a semiconductor device can be manufactured with highyield. In addition, a semiconductor device can be formed with highproductivity at low cost because a plating method is used for theformation of the conductive shield.

Embodiment 3

In this embodiment, another example of a semiconductor device forproviding high reliability and a method for manufacturing thesemiconductor device with the use of an embodiment of the presentinvention will be described with reference to FIGS. 22A to 22C, FIGS.23A1, 23A2, 23B1, and 23B2, and FIGS. 24A1 and 24A2. In the structure ofthis embodiment described below, a common reference numeral refers tothe same part or a part having a similar function throughout drawings,in Embodiment 1 and Embodiment 2, and the description thereof isomitted.

In this embodiment, an example of a method for manufacturing asemiconductor device having an electrode layer that penetrates theinside of the semiconductor device as illustrated in FIGS. 22B and 22Cin Embodiment 1 is described with reference to FIGS. 23A1, 23A2, 23B1,and 23B2, and FIGS. 24A1 and 24A2. FIGS. 23A2 and 23B2, and FIG. 24A2are plan views, and FIGS. 23A1 and 23B1, and FIG. 24A1 arecross-sectional views taken along line E-F of FIGS. 23A2 and 23B2, andFIG. 24A2, respectively.

A semiconductor device of this embodiment in a manufacturing process isillustrated in FIGS. 23A1, 23A2, 23B1, and 23B2. The first insulator 112and the second insulator 102 sandwich a plurality of semiconductorintegrated circuits 100 and a plurality of antennas 101, and form astack 144. The stack 144 includes a plurality of semiconductorintegrated circuits before separation into individual chips, andthrough-holes 189 are provided on outer sides of the semiconductorintegrated circuits in chip areas (see FIGS. 23A1 and 23A2). Note thatthe shape and number of the through-holes are not limited and can beselected as appropriate in accordance with a chip size and a shape. Forexample, a plurality of circular through-holes in a plan view(cylindrical through-hole in three dimensional view) may be provided.

The through-holes 189 penetrate the stack 144 and reach from the firstinsulator 112 to the second insulator 102. The through-holes 189 may beprocessed by physical treatment such as using a needle or a drill or maybe processed by chemical treatment such as etching. A laser beam is usedfor processing in this embodiment.

Next, the stack 144 having the through-holes 189 is subjected to aplating process. The stack 144 having the through-holes 189 is immersedin a plating solution including a metal material, and the conductiveshields 140 a and 104 b are formed on the surfaces of the stack 144 (seeFIGS. 23B1 and 23B2). Since the liquid plating solution attaches to theexposed surface of the stack 144, the conductive shields 140 a and 140 bare formed on the first insulator 112 side and the second insulator 102side, and the electrode layers 141 a and 141 b which function as throughelectrodes are also formed in the through-holes 189. The conductiveshields 140 a and 140 b are electrically connected to each other by theelectrode layers 141 a and 141 b. Note that the electrode layers 141 aand 141 b may be formed to fill the through-holes 189 or may be formedto cover side surfaces of the through-holes 189.

In this embodiment, the conductive shields 140 a and 140 b and theelectrode layers 141 a and 141 b are formed in the same plating process;therefore, the conductive shields 140 a and 140 b and the electrodelayers 141 a and 141 b are continuous films. The conductive shields 140a and 140 b and the electrode layers 141 a and 141 b may be formed inseparate processes or using different materials.

By a plating method, a region that can be treated at a time can belarge, productivity can be improved, and cost for a process can bereduced to achieve low cost.

The stack 144 in which the conductive shield 140 a and 140 b, and theelectrode layers 141 a and 141 b are formed is divided into individualsemiconductor integrated circuit chips 145 a, 145 b, 145 c, 145 d, 145e, and 145 f (see FIGS. 24A1 and 24A2). There is no particularlimitation on a separation means as long as physical separation ispossible, and separation is performed by laser beam irradiation in thisembodiment. Each of the semiconductor integrated circuit chips 145 a,145 b, and 145 c has the stack 143 which is formed by the separation ofthe stack 144. The semiconductor integrated circuit chip 145 bcorresponds to FIG. 22C. Note that a structure, like the semiconductorintegrated circuit chips 145 a and 145 c, may be used in which theelectrode layers 141 a and 141 b functioning as through electrodes areprovided, and side surfaces of the stack except a cut surface arecovered with the conductive shield. Through the above steps, asemiconductor device in which the conductive shield electricallyconnected to each other covers the periphery of the semiconductorintegrated circuit can be formed.

With the use of the conductive shield covering a semiconductorintegrated circuit, electrostatic breakdown (malfunctions of the circuitor damages of a semiconductor element) due to electrostatic discharge ofthe semiconductor integrated circuit is prevented. Further, by using apair of insulators between which the semiconductor integrated circuit issandwiched, a highly reliable semiconductor device that is reduced inthickness and size and has tolerance can be provided. In addition,defective shapes and defective characteristics due to the externalstress or an electrostatic discharge are prevented in the manufacturingprocess, so that a semiconductor device can be manufactured with highyield. In addition, a semiconductor device can be formed with highproductivity at low cost because a plating method is used for theformation of the conductive shield.

Embodiment 4

In this embodiment, an example of a plating method that is used for theformation of the conductive shield in a manufacturing process of asemiconductor device of an embodiment of the present invention will bedescribed. In the structure of this embodiment described below, a commonreference numeral refers to the same part or a part having a similarfunction throughout drawings, in Embodiment 1 and this embodiment, andthe description thereof is omitted.

In this embodiment, an example in which a conductive shield is formed byan electroless plating method will be described with reference to FIGS.26A to 26D.

The stack 143 in which the semiconductor integrated circuit 100 and theantenna 101 are sandwiched between the first insulator 112 and thesecond insulator 102 is formed in a manner similar to Embodiment 1 (seeFIG. 26A).

The electroless plating method is a wet plating method in whichelectrons are provided to metal ions in an aqueous solution that is aplating solution (there is the case of using an organic solvent) toperform reduction and deposit a metal thin film. The electroless platingmethod is a method in which metal is deposited by reduction action of ametal ion reducing agent.

Therefore, it is necessary that a body to be plated be catalyzed so thatdeposition reaction is performed. When the body to be plated itselfserves as a catalyst, catalyzation is not needed; however, a catalystmaterial is adsorbed by the surface of the body to be plated.

A catalyst material 170 is adsorbed by a region where the conductiveshield 140 is formed by a plating method in the stack 143 (see FIG.26B).

The catalyst material is appropriately selected depending on the platingmetal material. As the catalyst material, palladium (Pd), rhodium (Rh),ruthenium (Ru), osmium (Os), iridium (Ir), gold (Au), platinum (Pt),silver (Ag), or the like may be used. The catalyst material is dissolvedinto a solution, and is treated as a solution containing the catalystmaterial. In this embodiment, palladium is used for the catalystmaterial 170.

The stack 143 adsorbing the catalyst material 170 is immersed in aplating solution 171 including a plating metal material, and a filmincluding metal is grown on the catalyst material 170 (see FIG. 26C).The immersion time, temperature, or concentration of the platingsolution is controlled so as to obtain a desired film thickness and theconductive shield 140 is formed (see FIG. 26D).

The plating solution contains, as its main components, a metal salt (asalt containing a metal material to be deposited, typically, chloride orsulfate) and a reducing agent (which provides electrons to deposit metalions as metal). In addition, a pH adjuster, a buffer, a complexingagent, an accelerator, a stabilizer, an improver, or the like may beadded as an auxiliary component. With only the main components, metalions are deposited as metal under the right conditions such as pH andbath temperature. In contrast to the main components, the auxiliarycomponent functions to extend the life of a plating bath (platingsolution), to improve the efficiency of a reducing agent, and the like,and a highly economical electroless plating method can be performeddepending on selection of the auxiliary component. The pH adjusterinfluences a plating rate, reduction efficiency, and the state of acoating film by plating. The buffer (various organic acids or weakinorganic acids) suppresses pH fluctuation caused by a substancegenerated when metal deposition is caused by the reduction of metal ionsin an electroless plating method. The complexing agent contributes toprevention of hydroxide deposition in an alkaline solution and platingsolution decomposition, adjustment of free metal ion concentration andplating rate, and the like (typically, ammonia, ethylenediamine,pyrophosphate, a citric acid, an acetic acid, various organic salts, orthe like is used). The accelerator improves metal deposition efficiencyby suppressing generation of a hydrogen gas as well as accelerating theplating rate, which is added in minute amounts (typically, sulfide orfluoride is used). The stabilizer functions to suppress generation of areductive reaction in portions other than the surface of an object to beplated. The stabilizer suppresses natural decomposition of a platingbath or the like and prevents a deposition or the like generated withaging of a plating bath from reacting with the reducing agent, so as notto intensely generate a hydrogen gas (typically, chloride, sulfide,nitrate of lead or the like is used). The improver improves the state ofa coating film by plating and improves luster and the like (typically, asurfactant is used).

The conductive shield 140 which can be formed by an electroless platingmethod may be formed using an element selected from nickel, copper, tin,silver, gold, platinum, palladium, iron, cobalt, and tungsten; or analloy material including the element as its main component, for example.

As the alloy material, there are a nickel alloy (a nickel phosphorus(NiP) alloy, a nickel cobalt (NiCo) alloy, a nickel cobalt phosphorus(NiCoP) alloy, a nickel iron phosphorus (NiFeP) alloy, a nickel tungstenphosphorus (NiWP) alloy, and the like), and the like.

In this embodiment, a nickel phosphorus alloy film is formed by anelectroless plating method as the conductive shield 140. Although nickelis a magnetic substance, when phosphorus content is controlled to begreater than or equal to 11% as a nickel phosphorus alloy film, itsmagnetism can be decreased (disappear). Accordingly, the nickelphosphorus alloy film can be applied as the conductive shield 140without shortening the communication distance of the semiconductordevice.

By a plating method, a region that can be treated at a time can belarge, productivity can be improved, and cost for a process can bereduced to achieve low cost.

With the use of the conductive shield covering a semiconductorintegrated circuit, electrostatic breakdown (malfunctions of the circuitor damages of a semiconductor element) due to electrostatic discharge ofthe semiconductor integrated circuit is prevented. Further, by using apair of insulators between which the semiconductor integrated circuit issandwiched, a highly reliable semiconductor device that is reduced inthickness and size and has tolerance can be provided. In addition,defective shapes and defective characteristics due to the externalstress or an electrostatic discharge are prevented in the manufacturingprocess, so that a semiconductor device can be manufactured with highyield. In addition, a semiconductor device can be formed with highproductivity at low cost because a plating method is used for theformation of the conductive shield.

Note that this embodiment can be implemented in combination with any ofEmbodiments 1 to 4, as appropriate.

Embodiment 5

In this embodiment, an example of a plating method that is used for theformation of the conductive shield in a manufacturing process of asemiconductor device of an embodiment of the present invention will bedescribed. In the structure of this embodiment described below, a commonreference numeral refers to the same part or a part having a similarfunction throughout drawings, in Embodiment 1 and this embodiment, andthe description thereof is omitted.

In this embodiment, an example in which a conductive shield is formed byan electrolytic plating method will be described with reference to FIGS.25A to 25D.

The stack 143 in which the semiconductor integrated circuit 100 and theantenna 101 are sandwiched between the first insulator 112 and thesecond insulator 102 is formed in a manner similar to Embodiment 1 (seeFIG. 25A).

The electrolytic plating method is a wet plating method in whichelectrons are provided to metal ions in an aqueous solution that is aplating solution (there is the case of using an organic solvent) toperform reduction and deposit a metal thin film. The electrolyticplating method is a method in which metal ions are reduced withelectricity by flowing current and metal is deposited.

When an electrolytic plating method is utilized, a conductive film (alsoreferred to as a seed layer) through which current flows in a regionwhere a plating film is formed (a body to be plated) is necessary;therefore, a conductive film is formed on the insulator so that theconductive shield is formed on the insulator.

A conductive film 180 is formed in a region of the stack 143 where theconductive shield 140 is formed by a plating method (see FIG. 25B).

The conductive film 180 is appropriately selected depending on theplating metal material. It is preferable that the conductive film 180have conductivity and high adhesiveness with a plating film to beplated.

As the conductive film 180, a film of silver, copper, a nickel material,or a film of an alloy material thereof can be used. In this embodiment,as the conductive film 180, a copper film is formed by a sputteringmethod (with a thickness of 100 nm).

After pretreatment such as washing is performed, the stack 143 providedwith the conductive film 180 is immersed in a plating solution 181including a plating metal material and current flow to the conductivefilm 180, whereby a film including metal is grown on the conductive film180 (see FIG. 25C). The immersion time is controlled so as to obtain adesired film thickness and the conductive shield 140 is formed (see FIG.25D).

The plating solution contains, as its main components, a metal salt (asalt containing a metal material to be deposited, typically, chloride orsulfate) and a reducing agent (which provides electrons to deposit metalions as metal) in a manner similar to the electroless plating methoddescribed in Embodiment 4. In addition, a pH adjuster, a buffer, acomplexing agent, an accelerator, a stabilizer, an improver, or the likemay be added as an auxiliary component. In contrast to the maincomponent, the auxiliary component functions to extend the life of aplating bath (plating solution), to improve the efficiency of a reducingagent, and the like, and a highly economical electroless plating methodcan be performed depending on selection of the auxiliary component.

The conductive shield 140 formed by an electrolytic plating method maybe formed using an element selected from nickel, copper, tin, silver,gold, platinum, zinc, cadmium, chromium, iron, cobalt, and tungsten; oran alloy material containing the element as its main component, forexample.

As an alloy material, zinc alloys (a zinc iron alloy, a zinc nickelalloy, and a tin zinc alloy), tin alloys (a tin silver alloy and a tincobalt alloy), copper zinc alloys (brass), and the like can be given.

In this embodiment, a copper thin film is formed by an electrolyticplating method as the conductive shield 140. When the conductive shieldis formed on the insulator by an electrolytic plating method, there is astacked structure of the conductive shield 140 and the conductive film180. When the conductive shield is formed by an electrolytic platingmethod, the conductive film that is a seed layer also functions as aconductive shield; therefore, it may be said that conductive shield isformed by stacking the conductive film 180 and the conductive shield140.

By a plating method, a region that can be treated at a time can belarge, productivity can be improved, and cost for a process can bereduced to achieve low cost.

With the use of the conductive shield covering a semiconductorintegrated circuit, electrostatic breakdown (malfunctions of the circuitor damages of a semiconductor element) due to electrostatic discharge ofthe semiconductor integrated circuit is prevented. Further, by using apair of insulators between which the semiconductor integrated circuit issandwiched, a highly reliable semiconductor device that is reduced inthickness and size and has tolerance can be provided. In addition,defective shapes and defective characteristics due to the externalstress or an electrostatic discharge are prevented in the manufacturingprocess, so that a semiconductor device can be manufactured with highyield. In addition, a semiconductor device can be formed with highproductivity at low cost because a plating method is used for theformation of the conductive shield.

Note that this embodiment can be implemented in combination with any ofEmbodiments 1 to 4, as appropriate.

Embodiment 6

In this embodiment, a highly reliable semiconductor device and a methodfor manufacturing a semiconductor device with high yield will bedescribed in detail with reference to FIGS. 4A to 4C and FIGS. 5A and5B. In this embodiment, a complementary metal oxide semiconductor (CMOS)is described as an example of the semiconductor device.

Transistors 210 and 211 and insulating films 212 and 213, and aninsulating layer 214 are provided over a substrate 200 having aninsulating surface which is a formation substrate with a separationlayer 201 and an insulating film 202 functioning as a base filminterposed therebetween, so that the semiconductor integrated circuit250 is formed (see FIG. 4A).

The transistor 210 is a thin film transistor and includes source anddrain regions 224 a and 224 b, impurity regions 223 a and 223 b whoseconcentrations are lower than those of the source and drain regions 224a and 224 b, a channel formation region 226, a gate insulating layer227, a gate electrode layer 228, and insulating layers 229 a and 229 bfor forming a sidewall structure. The source and drain regions 224 a and224 b are in contact with and electrically connected to wiring layers230 a and 230 b respectively which function as source and drainelectrode layers. In this embodiment, the transistor 210 is a p-channelthin film transistor and the source and drain regions 224 a and 224 band the impurity regions 223 a and 223 b which are lightly doped drain(LDD) regions include impurity elements imparting p-type conductivity(e.g., boron (B), aluminum (Al), gallium (Ga), or the like).

The transistor 211 is a thin film transistor and includes source anddrain regions 204 a and 204 b, impurity regions 203 a and 203 b whoseconcentrations are lower than those of the source and drain regions 204a and 204 b, a channel formation region 206, a gate insulating layer207, a gate electrode layer 208, and insulating layers 209 a and 209 bfor forming a sidewall structure. The source and drain regions 204 a and204 b are in contact with and electrically connected to wiring layers210 a and 210 b respectively which function as source and drainelectrode layers. In this embodiment, the transistor 211 is an n-channelthin film transistor and the source and drain regions 204 a and 204 b,and the impurity regions 203 a and 203 b which are LDD regions includeimpurity elements imparting n-type conductivity (e.g., phosphorus (P),arsenic (As), or the like).

Next a conductive layer 263 functioning as an antenna is formed over theinsulating layer 214, and an inorganic insulating layer 254 is formed asa protective layer over the conductive layer 263. In this embodiment, asilicon nitride film is formed as the inorganic insulating layer 254.The conductive layer 263 is electrically connected to a semiconductorintegrated circuit 250.

As a first insulator 262, a structure body in which a fibrous body 280is impregnated with an organic resin 281 is used. The inorganicinsulating layer 254, the conductive layer 263, the semiconductorintegrated circuit 250, and the first insulator 262 are bonded, and theinorganic insulating layer 254, the conductive layer 263, and thesemiconductor integrated circuit 250 are separated from the substrate200 by using the separation layer 201. Therefore, the semiconductorintegrated circuit 250 is provided on the first insulator 262 side (seeFIGS. 4B and 4C).

Similarly to the first insulator 262, a structure body in which afibrous body 270 is impregnated with an organic resin 271 is used for asecond insulator 252.

The structure body is heated and subjected to pressure bonding, wherebythe second insulator 252 is bonded to the separation surface where thesemiconductor integrated circuit 250 is exposed, and the inorganicinsulating layer 254, the conductive layer 263, and the semiconductorintegrated circuit 250 are sandwiched between the first insulator 262and the second insulator 252 (see FIG. 5A).

Although not illustrated, a plurality of semiconductor integratedcircuits is sandwiched between the first insulator 262 and the secondinsulator 252, and then the semiconductor integrated circuits 250 areindividually divided, whereby semiconductor integrated circuit chips areformed. There is no particular limitation on a separation means as longas physical separation is possible, and separation is performed by laserbeam irradiation in this embodiment.

By separation, the conductive layer 263 and the semiconductor integratedcircuit 250 are sealed by the first insulator 262 and the secondinsulator 252, and divided surfaces (side surfaces generated byseparation) are formed on the chips.

A conductive shield 260 is formed by a wet plating method so as to covera stack in which the first insulator 262, the conductive layer 263, thesemiconductor integrated circuit 250, and the second insulator 252 arestacked (see FIG. 5B).

The conductive shield 260 may be formed on all the side surfaces tosurround (wrap) the periphery of the semiconductor device or may beformed to cover part of the side surfaces (divided surfaces). Theconductive shield 260 formed on an outer side of the first insulator 262is electrically connected to the conductive shield 260 formed on anouter side of the second insulator 252 in an embodiment of the presentinvention. In this embodiment, the conductive shield 260 is formed inthe same plating process on the outer sides of the first insulator 262and the second insulator 252, and is a continuous film.

By a plating method, a region that can be treated at a time can belarge, productivity can be improved, and cost for a process can bereduced to achieve low cost. Therefore, when the conductive shield isformed by using a plating method, a semiconductor device of anembodiment of the present invention can be formed with high productivityat low cost. Lower cost of a process allows a semiconductor device to beprovided at lower cost.

Accordingly, the conductive layer 263 and the semiconductor integratedcircuit 250 are sealed by the first insulator 262 and the secondinsulator 252, and are protected against electrostatic discharge byusing the conductive shield 260 provided on the outer sides of the firstinsulator 262 and the second insulator 252 which correspond to thesurface and back surface of the semiconductor device and on the cutsurface.

The conductive shield 260 transmits an electromagnetic wave that theconductive layer 263 which is an antenna included in the semiconductordevice should send and receive, and external static electricity isprevented from being applied to the semiconductor integrated circuit 250in the semiconductor device. The conductive shield 260 diffuses anddissipates static electricity applied by electrostatic discharge orprevents local existence (localization) of charge (not to generate localpotential difference); therefore, electrostatic breakdown of thesemiconductor integrated circuit 250 can be prevented.

Since the insulator and the conductive shield between which thesemiconductor integrated circuit is sandwiched are provided, an adverseeffect such as damage or deterioration of characteristics of thesemiconductor integrated circuit due to the external stress or anelectrostatic discharge can be prevented even in a manufacturingprocess. Accordingly, a semiconductor device can be formed with highyield.

The semiconductor device which is formed in this embodiment can be usedas a flexible semiconductor device by using a flexible insulator.

As a material for forming the semiconductor layer of the transistors 210and 211, an amorphous semiconductor (hereinafter also referred to as AS)manufactured using a semiconductor material gas typified by silane orgermane by a vapor deposition method or a sputtering method, apolycrystalline semiconductor formed by crystallizing the amorphoussemiconductor by utilizing light energy or thermal energy, amicrocrystalline (also referred to as semiamorphous or microcrystal)semiconductor (hereinafter also referred to as SAS), or the like can beused. The semiconductor layer can be formed by a sputtering method, anLPCVD method, a plasma CVD method, or the like.

The microcrystalline semiconductor film has a metastable state of anintermediate between an amorphous structure and a single crystalstructure when Gibbs free energy is considered. That is, themicrocrystalline semiconductor film is a semiconductor having a thirdstate which is stable in terms of free energy and has a short rangeorder and lattice distortion. Columnar-like or needle-like crystals growin a normal direction with respect to a substrate surface. The Ramanspectrum of microcrystalline silicon, which is a typical example of amicrocrystalline semiconductor, is located in lower wave numbers than520 cm⁻¹, which represents a peak of the Raman spectrum of singlecrystal silicon. That is, the peak of the Raman spectrum of themicrocrystalline silicon exists between 520 cm⁻¹ which represents singlecrystal silicon and 480 cm⁻¹ which represents amorphous silicon. Thesemiconductor includes hydrogen or halogen of at least 1 at. % toterminate dangling bonds. Moreover, a noble gas element such as helium,argon, krypton, or neon may be included to further promote latticedistortion, so that stability is enhanced and a favorablemicrocrystalline semiconductor film can be obtained.

The microcrystalline semiconductor film can be formed by ahigh-frequency plasma CVD method with a frequency of several tens toseveral hundreds of megahertz or a microwave plasma CVD apparatus with afrequency of greater than or equal to 1 GHz. The microcrystallinesemiconductor film can be typically formed using a dilution of siliconhydride or the like such as SiH₄, Si₂H₆, SiH₂Cl₂, SiHCl₃, SiCl₄, or SiF₄with hydrogen. With a dilution with one or plural kinds of noble gaselements of helium, argon, krypton, and neon in addition to siliconhydride or the like and hydrogen, the microcrystalline semiconductorfilm can be formed. In that case, the flow rate ratio of hydrogen tosilicon hydride or the like is set to be 5:1 to 200:1, preferably 50:1to 150:1, more preferably 100:1.

Hydrogenated amorphous silicon can be typically given as the amorphoussemiconductor, while a polysilicon and the like can be typically givenas a crystalline semiconductor. Examples of polysilicon (polycrystallinesilicon) include so-called high-temperature polysilicon that containspolysilicon formed at a process temperature greater than or equal to800° C. as its main component, so-called low-temperature polysiliconformed at a process temperature less than or equal to 600° C. thatcontains polysilicon as its main component, polysilicon obtained bycrystallizing amorphous silicon by using an element that promotescrystallization, and the like. Naturally, as described above, amicrocrystalline semiconductor, or a semiconductor which includes acrystalline phase in a portion of a semiconductor layer can be used.

As a material of the semiconductor, as well as elementary substance ofsilicon (Si), germanium (Ge), or the like, a compound semiconductor suchas GaAs, InP, SiC, ZnSe, GaN, or SiGe can be used. Alternatively, anoxide semiconductor such as zinc oxide (ZnO), tin oxide (SnO₂),magnesium zinc oxide, gallium oxide, or indium oxide, an oxidesemiconductor formed of any of the above oxide semiconductors, or thelike may be used. For example, an oxide semiconductor formed of ZnO,indium oxide, and gallium oxide may be used. In the case of using ZnOfor the semiconductor layer, a gate insulating layer is preferablyformed using Y₂O₃, Al₂O₃, TiO₂, or a stack of any of the above. For thegate electrode layer, the source electrode layer, and the drainelectrode layer, ITO, Au, Ti, or the like is preferably used.Alternatively, ZnO to which In, Ga, or the like is added may be used.

In the case of using a crystalline semiconductor layer for thesemiconductor layer, the crystalline semiconductor layer may be formedby various methods (such as a laser crystallization method, a thermalcrystallization method, or a thermal crystallization method using anelement which promotes crystallization, such as nickel). Also, amicrocrystalline semiconductor, which is an SAS, can be crystallized bylaser irradiation to increase its crystallinity. In the case where theelement which promotes crystallization is not used, before the amorphoussilicon film is irradiated with a laser beam, the amorphous silicon filmis heated at 500° C. for one hour in a nitrogen atmosphere to dischargehydrogen so that the hydrogen concentration in the amorphous siliconfilm becomes less than or equal to 1×10²⁰ atoms/cm³. This is because theamorphous silicon film is destroyed when the amorphous silicon filmcontaining a high amount of hydrogen is irradiated with a laser beam.

The crystallization may be performed by adding an element which promotescrystallization (also referred to as a catalyst element or a metalelement) to an amorphous semiconductor layer and performing a heattreatment (at 550° C. to 750° C. for 3 minutes to 24 hours) in acrystallization step in which the amorphous semiconductor layer iscrystallized to form a crystalline semiconductor layer. The elementwhich promotes the crystallization can be one or more of iron (Fe),nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd),osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au).

A technique for introducing a metal element into an amorphoussemiconductor layer is not particularly limited as long as it is atechnique capable of providing the metal element on a surface or insideof the amorphous semiconductor layer. For example, a sputtering method,a CVD method, a plasma processing method (including a plasma CVDmethod), an adsorption method, or a method for coating a solution ofmetal salt, can be used. In the above processes, the method using asolution is convenient and has an advantage of easily adjusting theconcentration of a metal element. In addition, in order to improve thewettability of the surface of the amorphous semiconductor layer tospread an aqueous solution on the entire surface of the amorphoussemiconductor layer, an oxide film is preferably formed by UV lightirradiation in an oxygen atmosphere, thermal oxidation, treatment usingozone water containing hydroxy radical or hydrogen peroxide solution, orthe like.

In order to remove or reduce the element that promotes crystallizationfrom the crystalline semiconductor layer, a semiconductor layercontaining an impurity element is formed in contact with the crystallinesemiconductor layer and used as a gettering sink. The impurity elementmay be an impurity element imparting n-type conductivity, an impurityelement imparting p-type conductivity, a noble gas element, or the like.For example, one or plural elements selected from phosphorus (P),nitrogen (N), arsenic (As), antimony (Sb), bismuth (Bi), boron (B),helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) can beused. The semiconductor layer containing a noble gas element is formedover the crystalline semiconductor layer containing an element whichpromotes crystallization, and heat treatment (at 550° C. to 750° C. for3 minutes to 24 hours) is performed. The element which promotescrystallization in the crystalline semiconductor layer moves into thesemiconductor layer containing a noble gas element, and the elementwhich promotes crystallization in the crystalline semiconductor layer isremoved or reduced. Then, the semiconductor layer containing a noble gaselement, which serves as a gettering sink, is removed.

The amorphous semiconductor layer may be crystallized by using acombination of heat treatment and laser irradiation treatment. The heattreatment or the laser irradiation treatment may be carried out severaltimes, separately.

Also, a crystalline semiconductor layer may be formed over a substratedirectly by a plasma method. Alternatively, the crystallinesemiconductor layer may be selectively formed over a substrate by usinga plasma method.

The gate insulating layers 207 and 227 may be formed using siliconoxide, or may be formed with a stacked structure of silicon oxide andsilicon nitride. The gate insulating layers 207 and 227 may be formed bydepositing an insulating film by a plasma CVD method or a low pressureCVD method or may be formed by solid-phase oxidation or solid-phasenitridation by plasma treatment. This is because a gate insulating layerformed by oxidizing or nitriding a single crystal semiconductor layer byplasma treatment is dense, has high withstand voltage, and is highlyreliable. For example, the surface of the semiconductor layer isoxidized or nitrided using nitrous oxide (N₂O) diluted with Ar by 1 to 3times (flow ratio) by application of a microwave (2.45 GHz) power of 3kW to 5 kW at a pressure of 10 Pa to 30 Pa. By this process, aninsulating film of 1 nm to 10 nm (preferably, 2 nm to 6 nm) thick isformed. Further, nitrous oxide (N₂O) and silane (SiH₄) are introduced,and a silicon oxynitride film is formed by a vapor deposition method byapplication of a microwave (2.45 GHz) power of 3 kW to 5 kW at apressure of 10 Pa to 30 Pa; accordingly, the gate insulating layer isformed. The combination of the solid-phase reaction and the reaction bythe vapor deposition method can form a gate insulating layer with a lowinterface state density and an excellent withstand voltage.

As the gate insulating layers 207 and 227, a high dielectric constantmaterial such as zirconium dioxide, hafnium oxide, titanium dioxide, ortantalum pentoxide may be used. When a high dielectric constant materialis used for the gate insulating layers 207 and 227, gate leakage currentcan be reduced.

The gate electrode layers 208 and 228 can be formed using a CVD method,a sputtering method, a droplet discharging method, and the like. Thegate electrode layer may be formed of an element selected from Ag, Au,Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, andBa; or an alloy material or a compound material containing any of theelements as its main component. Alternatively, a semiconductor filmtypified by a polycrystalline silicon film doped with an impurityelement such as phosphorus, or an AgPdCu alloy may be used. Further,either a single-layer structure or a multi-layer structure may be used;for example, a two-layer structure of a tungsten nitride film and amolybdenum film may be used or a three-layer structure in which atungsten film with a thickness of 50 nm, a film of an aluminum-silicon(Al—Si) alloy film with a thickness of 500 nm, and a titanium nitridefilm with a thickness of 30 nm are stacked in this order may be used. Inthe case of the three-layer structure, a tungsten nitride film may beused instead of the tungsten film as the first conductive film, analuminum-titanium (Al—Ti) alloy film may be used instead of thealuminum-silicon (Al—Si) alloy film as the second conductive film, and atitanium film may be used instead of the titanium nitride film as thethird conductive film.

A light-transmitting material which transmits visible light can also beused for the gate electrode layers 208 and 228. As thelight-transmitting conductive material, indium tin oxide (ITO), indiumtin oxide containing silicon oxide (ITSO), organoindium, organotin, zincoxide, or the like can be used. Alternatively, indium zinc oxide (IZO)containing zinc oxide (ZnO), zinc oxide (ZnO), ZnO doped with gallium(Ga), tin oxide (SnO₂), indium oxide containing tungsten oxide, indiumzinc oxide containing tungsten oxide, indium oxide containing titaniumoxide, indium tin oxide containing titanium oxide, or the like may beused.

If etching processing is required to form the gate electrode layers 208and 228, a mask may be formed and dry etching or wet etching may beperformed. The electrode layers can be etched into tapered shapes by aninductively coupled plasma (ICP) etching method with the etchingcondition (the amount of electric power applied to a coiled electrode,the amount of electric power applied to an electrode on a substrateside, the temperature of the electrode on the substrate side, or thelike) appropriately adjusted. Note that a gas including chlorinetypified by Cl₂, BCl₃, SiCl₄, and CCl₄; a gas including fluorinetypified by CF₄, SF₆, and NF₃; or O₂ can be appropriately used for theetching gas.

The insulating layers 209 a, 209 b, 229 a, and 229 b for forming asidewall structure may be formed in a self-aligning manner by forming aninsulating layer, which covers the gate electrode layers and thesemiconductor layers, and processing the insulating layer by anisotropicetching using a reactive ion etching (RIE) method. Here, the insulatinglayer is not particularly limited, but is preferably formed usingsilicon oxide which is formed by reacting tetraethyl orthosilicate(TEOS), silane, or the like and oxygen, nitrous oxide, or the like andhas favorable step coverage. The insulating layer can be formed by athermal CVD method, a plasma CVD method, an atmospheric pressure CVDmethod, a bias ECRCVD method, a sputtering method, or the like.

Although a single gate structure is described in this embodiment, amulti-gate structure such as a double-gate structure may also be used.In this case, gate electrode layers may be provided above and below thesemiconductor layer or a plurality of gate electrode layers may beprovided only on one side (above or below) of the semiconductor layer.

Alternatively, silicides may be provided in the source and drain regionsof the transistor. The silicides are formed by forming conductive filmson the source and drain regions of the semiconductor layer and makingsilicon in the semiconductor layer in the source and drain regions ofthe semiconductor layer which used to be exposed and the conductive filmreact by heat treatment, a GRTA method, an LRTA method, or the like.Alternatively, a silicide may be formed by light irradiation using laserirradiation or a lamp. As a material of the conductive film used forforming a silicide, the following can be used: titanium (Ti), nickel(Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr),hafnium (Hf), tantalum (Ta), vanadium (V), neodymium (Nd), chromium(Cr), platinum (Pt), palladium (Pd), or the like.

The wiring layers 210 a, 210 b, 230 a, and 230 b which function assource electrode layers and drain electrode layers can be formed bydepositing a conductive film by a PVD method, a CVD method, anevaporation method, or the like, and then etching the conductive filminto desired shapes. Alternatively, the wiring layers can be formedselectively at a predetermined place by a printing method, anelectroplating method, or the like. Further, a reflow method or adamascene method may be used as well. As a material of the wiring layers210 a, 210 b, 230 a, and 230 b, metal such as Ag, Au, Cu, Ni, Pt, Pd,Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, or Ba; or a semiconductorsuch as Si or Ge or an alloy thereof, or nitride thereof may be used.Further, a light-transmitting material can also be used.

As the light-transmitting conductive material, indium tin oxide (ITO),indium tin oxide containing silicon oxide (ITSO), indium zinc oxide(IZO) containing zinc oxide (ZnO), zinc oxide (ZnO), ZnO doped withgallium (Ga), tin oxide (SnO₂), indium oxide containing tungsten oxide,indium zinc oxide containing tungsten oxide, indium oxide containingtitanium oxide, indium tin oxide containing titanium oxide, or the likecan be used.

For each of the insulating films 212 and 213 and the insulating layer214, an inorganic insulating material such as silicon oxide, siliconnitride, silicon oxynitride, aluminum oxide, aluminum nitride, oraluminum oxynitride can be used.

With the use of the conductive shield covering a semiconductorintegrated circuit, electrostatic breakdown (malfunctions of the circuitor damages of a semiconductor element) due to electrostatic discharge ofthe semiconductor integrated circuit is prevented. Further, by using apair of insulators between which the semiconductor integrated circuit issandwiched, a highly reliable semiconductor device that is reduced inthickness and size and has tolerance can be provided. In addition,defective shapes and defective characteristics due to the externalstress or an electrostatic discharge are prevented in the manufacturingprocess, so that a semiconductor device can be manufactured with highyield.

The semiconductor device according to an embodiment of the presentinvention can be applied to a storage element or the like using asemiconductor layer as well as a field effect transistor, as asemiconductor element, so that semiconductor devices having functionsnecessary for a variety of uses can be manufactured and provided.

Note that this embodiment can be implemented in combination with any ofEmbodiments 1 to 5, as appropriate.

Embodiment 7

In this embodiment, an example of a semiconductor device having a memorywill be described as a semiconductor device with high reliability and amanufacturing method thereof, with reference to FIGS. 6A to 6E, FIGS. 7Ato 7C, and FIGS. 8A and 8B.

A semiconductor device of this embodiment includes a memory including amemory cell array and a driver circuit portion which drives the memorycell array.

A separation layer 301 is formed over a substrate 300 which is aformation substrate having an insulating surface, and an insulating film302 functioning as a base film is formed over the separation layer 301.

Then, a semiconductor film is formed over the insulating film 302. Thesemiconductor film may be formed by a sputtering method, an LPCVDmethod, a plasma CVD method or the like to be 25 nm to 200 nm thick(preferably, 30 nm to 150 nm thick).

In this embodiment, an amorphous semiconductor film is formed over theinsulating film 302, and the amorphous semiconductor film iscrystallized by laser irradiation; accordingly, a semiconductor filmthat is a crystalline semiconductor film is formed.

The semiconductor film obtained as described above may be selectivelydoped with the slight amount of impurity elements (boron or phosphorus)for controlling threshold voltage of a thin film transistor. This dopingof impurity elements may be performed against the amorphoussemiconductor film before crystallization. When the amorphoussemiconductor film is doped with impurity elements, the impurities canbe activated by heat treatment for crystallization later. Further, adefect and the like generated at the doping can be improved as well.

Next, the semiconductor film is shaped into a desired shape using amask. In this embodiment, after an oxide film formed on thesemiconductor film is removed, another oxide film is formed. Then, aphotomask is formed, and semiconductor layers 303, 304, 305, and 306 areformed by processing using a photolithography method. For end portionsof the semiconductor layers, inclination angles (taper angles) may beprovided.

The etching may be carried out by either plasma etching (dry etching) orwet etching. For treating a large-sized substrate, plasma etching issuitable. As an etching gas, a gas containing fluorine or chlorine suchas CF₄, NF₃, Cl₂, or BCl₃ is used, and an inert gas such as He or Ar maybe added thereto, as appropriate. If the etching is carried oututilizing atmospheric pressure discharge, electric discharge processingcan be carried out locally, and a mask does not need to be formed overthe entire surface of the substrate.

An insulating film 310 is formed over the semiconductor layer 305. Theinsulating film 310 may be formed using silicon oxide or a stackedstructure of silicon oxide and silicon nitride. The insulating film 310may be formed by depositing the insulating layer by a plasma CVD methodor a low pressure CVD method; however, the insulating film 310 ispreferably formed by being subjected to solid-phase oxidation orsolid-phase nitridation by plasma treatment. This is because aninsulating layer which is formed through oxidation or nitridation of thesemiconductor layer (typically, a silicon layer) by plasma treatment hasa dense film quality, high withstand voltage, and high reliability. Theinsulating film 310 is used as a tunnel insulating layer for injectingcharges into a charge accumulating layer 311; therefore, a stronginsulating layer is preferable. The insulating film 310 is preferablyformed with a thickness of 1 nm to 20 nm, and preferably 3 nm to 6 nm.

The insulating film 310 is preferably formed by plasma treatment in sucha way that, for example, a silicon oxide layer is formed with athickness of 3 nm to 6 nm on the semiconductor layer by plasma treatmentunder an oxygen atmosphere, and a nitrogen-plasma-treated layer isformed by treating the surface of the silicon oxide layer with nitrogenplasma under a nitrogen atmosphere. Specifically, first, a silicon oxidelayer with a thickness of 3 nm to 6 nm is formed on the semiconductorlayer by plasma treatment under an oxygen atmosphere. Subsequently, anitrogen plasma treated layer with a high concentration of nitrogen isformed over the surface or near the surface of the silicon oxide layerby performance of plasma treatment under a nitrogen atmospheresuccessively. Note that “near the surface” refers to a depth ofapproximately 0.5 nm to 1.5 nm from a surface of a silicon oxide layer.For example, by conducting plasma treatment under a nitrogen atmosphere,a structure is obtained in which the silicon oxide layer contains 20atomic % to 50 atomic % nitrogen in a region from the surface to a depthof about 1 nm.

A surface of a silicon layer as a typical example of the semiconductorlayer is oxidized by plasma treatment, whereby a dense oxide layer thathas no distortion in an interface can be formed. In addition, throughnitridation by plasma treatment of the oxide layer, oxygen on a portionof a surface is replaced with nitrogen and a nitride layer is formed,whereby the layer can be made even denser. Consequently, an insulatinglayer which has high withstand voltage can be formed.

In any event, through use of the aforementioned solid-phase oxidation orsolid-phase nitridation by plasma treatment, even if a glass substratewith a heat resistance temperature of less than or equal to 700° C. isused, an insulating layer equal to a thermal oxidation film that isformed at a temperature of from 950° C. to 1050° C. can be obtained.That is, a tunnel insulating layer having high reliability can be formedas the tunnel insulating layer of a nonvolatile memory element.

The charge accumulation layer 311 is formed over the insulating film310. The charge accumulation layer 311 may be provided as either asingle layer or stacked layers.

The charge accumulation layer 311 can be a floating gate formed of alayer or particles of a semiconductor material or a conductive material.As the semiconductor material, silicon, silicon germanium, and the likecan be given. When silicon is used, amorphous silicon or polysilicon canbe used. Further, polysilicon doped with phosphorus can also be used. Asthe conductive material, an element selected from tantalum (Ta),titanium (Ti), molybdenum (Mo), or tungsten (W); an alloy containing theabove element as its main component; an alloy film in which the aboveelements are combined (typically, an Mo—W alloy film or an Mo—Ta alloyfilm); or a silicon film provided with conductivity may be used. Underthe conductive layer formed of such a material, nitride such as tantalumnitride, tungsten nitride, titanium nitride, or molybdenum nitride; orsilicide such as tungsten silicide, titanium silicide, or molybdenumsilicide may be formed. Furthermore, a stacked structure of the abovesemiconductor materials, conductive materials, or the semiconductormaterial and the conductive material may be employed. For example, astacked structure of a silicon layer and a germanium layer may beemployed.

Alternatively, the charge accumulation layer 311 can be formed as aninsulating layer having a trap that holds charges. As a typical exampleof such a material, a silicon compound and a germanium compound aregiven. As the silicon compound, silicon nitride, silicon oxynitride,silicon oxynitride to which hydrogen is added, and the like can begiven. As examples of the germanium compound, germanium nitride,germanium nitride to which oxygen is added, germanium oxide to whichnitrogen is added, germanium nitride to which oxygen and hydrogen areadded, germanium oxide to which nitrogen and hydrogen are added, and thelike can be given.

Next, masks which cover the semiconductor layers 303, 304, and 306 areformed. Using the masks and the charge accumulation layer 311 as masks,an impurity element imparting n-type conductivity is added to formn-type impurity regions 362 a and 362 b. In this embodiment, phosphorus(P), which is an impurity element imparting n-type conductivity, is usedas the impurity element. Here, doping is performed so that the n-typeimpurity regions 362 a and 362 b each contain the impurity elementimparting n-type conductivity at a concentration of about 1×10¹⁷atoms/cm³ to 5×10¹⁸ atoms/cm³. The masks which cover the semiconductorlayers 303, 304, and 306 are removed.

An oxide film over the semiconductor layer 306 is removed, and a gateinsulating layer 309 which covers the semiconductor layers 305 and 306,the insulating film 310, and the charge accumulation layer 311 isformed. When the gate insulating layer 309 is thick in the memory cellarray, the thin film transistor and the memory element can have hightolerance to high voltage; accordingly reliability can be enhanced.

Note that although the gate insulating layer 309 formed over thesemiconductor layer 305 functions as a control insulating layer of amemory element which is completed later, the gate insulating layer 309formed over the semiconductor layer 306 functions as a gate insulatinglayer of the thin film transistor. Therefore, the layer is called thegate insulating layer 309 in this specification.

The oxide film over the semiconductor layers 303 and 304 is removed, andthen a gate insulating layer 308, which covers the semiconductor layers303 and 304, is formed (see FIG. 6A). The gate insulating layer 308 canbe formed using a plasma CVD method, a sputtering method, or the like.The thickness of the gate insulating layer 308 included in the thin filmtransistor, which is provided in the driver circuit portion, ispreferably greater than or equal to 1 nm and less than or equal to 10nm, and more preferably, about 5 nm. Thinning of the gate insulatinglayer 308 has an effect of driving the transistor in the driver circuitportion at high speed and low voltage.

The gate insulating layer 308 may be formed using silicon oxide or astacked structure of silicon oxide and silicon nitride. The gateinsulating layer 308 may be formed by depositing an insulating film by aplasma CVD method or a low pressure CVD method or may be formed bysolid-phase oxidation or solid-phase nitridation by plasma treatment.This is because a gate insulating layer formed by oxidizing or nitridinga semiconductor layer by plasma treatment is dense, and has highwithstand voltage and excellent reliability.

As the gate insulating layer 308, a high dielectric constant materialmay be used. When a high dielectric constant material is used for thegate insulating layer 308, gate leakage current can be reduced. As thehigh dielectric constant material, zirconium dioxide, hafnium oxide,titanium dioxide, tantalum pentoxide, or the like can be used. Further,a silicon oxide layer may be formed by solid-phase oxidation by plasmatreatment.

Further, a thin silicon oxide film can also be formed by oxidizing thesurface of the semiconductor region by a GRTA method, an LRTA method, orthe like, thereby forming a thermal oxide film. Accordingly, a thinsilicon oxide film may be formed. Note that a noble gas element such asargon is preferably included in a reactive gas and is preferably mixedin the insulating film to be formed in order to form a dense insulatingfilm with few gate leakage current at a low film-formation temperature.

Then, a first conductive film having a thickness of 20 nm to 100 nm anda second conductive film having a thickness of 100 nm to 400 nm, each ofwhich serves as a gate electrode layer, are stacked over the gateinsulating layers 308 and 309. The first and second conductive films canbe formed by a sputtering method, an evaporation method, a CVD method,or the like. The first and second conductive films may be formed usingan element selected from tantalum (Ta), tungsten (W), titanium (Ti),molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), andneodymium (Nd), or an alloy or compound material containing the abovematerial as its main component. Alternatively, the first and secondconductive films may be formed using a semiconductor film typified by apolycrystalline silicon film doped with an impurity element such asphosphorus, or an AgPdCu alloy film. The conductive film is not limitedto the two-layer structure, and, for example, may have a three-layerstructure in which a tungsten film with a thickness of 50 nm, analuminum and silicon (Al—Si) alloy film with a thickness of 500 nm, anda titanium nitride film with a thickness of 30 nm are sequentiallystacked. In the case of the three-layer structure, a tungsten nitridefilm may be used instead of the tungsten film as the first conductivefilm, an aluminum-titanium (Al—Ti) alloy film may be used instead of thealuminum-silicon (Al—Si) alloy film as the second conductive film, and atitanium film may be used instead of the titanium nitride film as thethird conductive film. Alternatively, a single-layer structure may beadopted as well. In this embodiment, tantalum nitride is formed to havea thickness of 30 nm for the first conductive film, and tungsten (W) isformed to have a thickness of 370 nm for the second conductive film.

The first and second conductive films are etched to form first gateelectrode layers 312, 313, and 314, second gate electrode layers 316,317, and 318, a first control gate electrode layer 315, and a secondcontrol gate electrode layer 319 (see FIG. 6B).

In this embodiment, an example is illustrated in which the first gateelectrode layer and the second gate electrode layer (the first controlgate electrode layer and the second control gate electrode layer) areformed to have perpendicular side surfaces; however, an embodiment ofthe present invention is not limited to this. Both the first gateelectrode layer and the second gate electrode layer (the first controlgate electrode layer and the second control gate electrode layer) mayhave tapered shapes, or one of the first gate electrode layer or thesecond gate electrode layer (the first control gate electrode layer orthe second control gate electrode layer) may have a tapered shape whilethe other may have a perpendicular side surface by anisotropic etching.The taper angles may be different or equal among the stacked gateelectrode layers. With a tapered shape, coverage of a film to be stackedthereover is improved and a defect is reduced, which leads to improvingreliability.

The gate insulating layers 308 and 309 may be etched to some extent andthinned (so-called film reduction) by the etching step in forming thegate electrode layers (and the control gate electrode layers).

Next, masks 321 and 363 which cover the semiconductor layers 304, 305and 306 are formed. An impurity element 320 imparting p-typeconductivity is added using the masks 321 and 363, the first gateelectrode layer 312, and the second gate electrode layer 316 as masks toform p-type impurity regions 322 a and 322 b. In this embodiment, boron(B) is used as the impurity element. Here, doping is performed so thatthe p-type impurity regions 322 a and 322 b contain the impurity elementimparting p-type conductivity at a concentration of about 1×10²⁰atoms/cm³ to about 5×10²¹ atoms/cm³. In addition, a channel formationregion 323 is formed in the semiconductor layer 303 (see FIG. 6C).

The p-type impurity regions 322 a and 322 b are high-concentrationp-type impurity regions and serve as a source region and a drain region.

Next, a mask 325, which covers the semiconductor layer 303, is formed.An n-type impurity element 324 is added using the mask 325, the firstgate electrode layer 313, the second gate electrode layer 317, the firstgate electrode layer 314, the second gate electrode layer 318, the firstcontrol gate electrode layer 315, and the second control gate electrodelayer 319 as masks, so that n-type impurity regions 326 a, 326 b, 327 a,327 b, 328 a, and 328 b are formed. In this embodiment, phosphorus (P)is used as the impurity element. Here, doping is performed so that eachof the n-type impurity regions 326 a, 326 b, 327 a, 327 b, 328 a and 328b contains the impurity element imparting n-type conductivity at aconcentration of about 5×10¹⁹ atoms/cm³ to about 5×10²⁰ atoms/cm³. Achannel formation region 329, a channel formation region 330 and n-typeimpurity regions 364 a, 364 b, and a channel formation region 331 areformed in the semiconductor layer 304, the semiconductor layer 305, andthe semiconductor layer 306, respectively (see FIG. 6D).

The n-type impurity regions 326 a, 326 b, 327 a, 327 b, 328 a, and 328 bare n-type high-concentration impurity regions and function as sourceregions and drain regions. On the other hand, the n-type impurityregions 364 a and 364 b are low-concentration impurity regions andfunction as LDD regions.

The mask 325 is removed by O₂ ashing or with a resist stripper, and anoxide film is also removed. After that, an insulating film, namely asidewall may be formed so as to cover side surfaces of the gateelectrode layers. The sidewall may be formed of an insulating filmcontaining silicon by a plasma CVD method or a low pressure CVD (LPCVD)method.

In order to activate the impurity element, heat treatment, strong lightirradiation, or laser beam irradiation may be performed. At the sametime as the activation, a plasma damage to the gate insulating layer andto an interface between the gate insulating layer and the semiconductorlayer can be repaired.

Subsequently, an interlayer insulating layer which covers the gateinsulating layers and the gate electrode layers is formed. In thisembodiment, a stacked structure of insulating films 367 and 368 is used.The insulating films 367 and 368 each may be a silicon nitride film, asilicon nitride oxide film, a silicon oxynitride film, or a siliconoxide film formed by a sputtering method or plasma CVD. Alternatively,another insulating film containing silicon may be employed to form asingle-layer structure or a stacked structure including three or morelayers.

Further, heat treatment is performed in a nitrogen atmosphere at 300° C.to 550° C. for 1 hour to 12 hours, whereby the semiconductor layer ishydrogenated. Preferably, this step is performed at 400° C. to 500° C.Through this step, dangling bonds in the semiconductor layer can beterminated by hydrogen contained in the insulating film 367 that is aninterlayer insulating layer. In this embodiment, heat treatment isperformed at 410° C. for one hour.

Each of the insulating film 367 and the insulating film 368 can beformed using a material selected from aluminum nitride (AlN), aluminumoxynitride (AlON), aluminum nitride oxide (AlNO) containing morenitrogen than oxygen, aluminum oxide, diamond-like carbon (DLC),nitrogen-containing carbon (CN), and other substance including aninorganic insulating material. In addition, a siloxane resin may also beused. The siloxane resin corresponds to a resin including Si—O—Sibonding.

Next, using a resist mask, contact holes (openings) that reach thesemiconductor layers are formed in the insulating films 367 and 368, andthe gate insulating layers 308 and 309. Etching may be performed once ora plurality of times according to a selection ratio of the materialswhich are used. Etching is performed to remove the insulating film 368,the insulating film 367, the gate insulating layers 308 and 309, so thatthe openings that reach the p-type impurity regions 322 a and 322 b, then-type impurity region 326 a, 326 b, 327 a, 327 b, 328 a, and 328 b,which are source regions and drain regions, are formed. For the etching,wet etching, dry etching, or the both may be employed. A hydrofluoricacid-based solution such as a mixed solution of ammonium hydrogenfluoride and ammonium fluoride may be used as an etchant of wet etching.As an etching gas for dry etching, a chlorine-based gas typified by Cl₂,BCl₃, SiCl₄, CCl₄, or the like; a fluorine-based gas typified by CF₄,SF₆, NF₃, or the like; or O₂ can be used as appropriate. Further, aninert gas may be added to an etching gas. As an inert element to beadded, one or plural elements selected from He, Ne, Ar, Kr, and Xe canbe used.

A conductive film is formed so as to cover the openings, and theconductive film is etched to form wiring layers 369 a, 369 b, 370 a, 370b, 371 a, 371 b, 372 a, and 372 b, which are source and drain electrodelayers electrically connected to portions of respective source and drainregions. The wiring layers can be formed by forming the conductive filmby a PVD method, a CVD method, an evaporation method, or the like, andthen etching the conductive film into a desired shape. In addition, aconductive layer can be selectively formed in a predetermined positionby a droplet discharge method, a printing method, an electrolyticplating method, or the like. Further, a reflow method or a damascenemethod may be used as well. As a material for the source electrode layeror the drain electrode layer, metal such as Ag, Au, Cu, Ni, Pt, Pd, Ir,Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, or Ba; or Si or Ge; an alloy ornitride thereof can be used. Further, a stacked structure of these maybe used. In this embodiment, titanium (Ti) is formed to be 60 nm thick,a titanium nitride film is formed to be 40 nm thick, aluminum is formedto be 700 nm thick, and titanium (Ti) is formed to be 200 nm thick, andthen the stacked film is processed into a desired shape.

Through the above steps, a semiconductor integrated circuit 350 can bemanufactured, in which a p-channel thin film transistor 373 having ap-type impurity region and an n-channel thin film transistor 374 havingan n-type impurity region are provided in the driver circuit portion;and a memory element 375 having an n-type impurity region and ann-channel thin film transistor 376 having an n-type impurity region areprovided in the memory cell array (see FIG. 6E).

In this embodiment, the semiconductor integrated circuit 350 is providedwith an insulating layer 390 (see FIG. 7A). Next, a conductive layer 380functioning as an antenna is formed over the insulating layer 390, andan inorganic insulating layer 381 is formed as a protective layer overthe conductive layer 380 (see FIG. 7B).

A structure body in which a fibrous body 386 is impregnated with anorganic resin 387 is used as a first insulator 382. The structure bodyis heated and subjected to pressure bonding, and the semiconductorintegrated circuit 350, the first insulator 382, and a fourth insulator391 are bonded. The separation layer 301 is used, and the semiconductorintegrated circuit 350 is separated from the substrate 300. Accordingly,the semiconductor integrated circuit 350 is provided on the firstinsulator 382 side (see FIG. 7C).

Similarly to the first insulator 382, a structure body in which thefibrous body 386 is impregnated with the organic resin 387 is used for asecond insulator 385. The structure body is heated and subjected topressure bonding, so that a third insulator 388 and the second insulator385 are bonded to each other. A bonding layer 389 is provided on onesurface of the third insulator 388 that is bonded to the semiconductorintegrated circuit 350, on which the second insulator 385 is notprovided.

The bonding layer 389 is bonded to the separation surface where thesemiconductor integrated circuit 350 is exposed, and the semiconductorintegrated circuit 350 is sandwiched by the fourth insulator 391, thefirst insulator 382, and the third insulator 388 and the secondinsulator 385 (see FIG. 8A).

Although not illustrated, a plurality of semiconductor integratedcircuits is sandwiched between the first insulator 382 and the secondinsulator 385, and then the semiconductor integrated circuits 350 areindividually divided, whereby semiconductor integrated circuit chips areformed. There is no particular limitation on a separation means as longas physical separation is possible, and separation is performed by laserbeam irradiation in this embodiment. By separation, the conductive layer380 and the semiconductor integrated circuit 350 are sealed by the firstinsulator 382 and the second insulator 385 and divided surfaces (sidesurfaces to be generated by separation) are generated for the chips.

A conductive shield 395 is formed by a wet plating method so as to covera stack in which the first insulator 382, the conductive layer 380, thesemiconductor integrated circuit 350, and the second insulator 385 arestacked (see FIG. 8B).

The conductive shield 395 may be formed on all the side surfaces tosurround (wrap) the periphery of the semiconductor device or may beformed to cover part of the side surfaces (divided surfaces). Theconductive shield 395 formed on an outer side of the first insulator 382is electrically connected to the conductive shield 395 formed on anouter side of the second insulator 385 in an embodiment of the presentinvention. In this embodiment, the conductive shield 395 is formed inthe same plating process on the outer sides of the first insulator 382and the second insulator 385, and is a continuous film.

By a plating method, a region that can be treated at a time can belarge, productivity can be improved, and cost for a process can bereduced to achieve low cost. Therefore, when the conductive shield isformed by using a plating method, a semiconductor device of anembodiment of the present invention can be formed with high productivityat low cost. Lower cost of a process allows a semiconductor device to beprovided at lower cost.

Accordingly, the conductive layer 380 and the semiconductor integratedcircuit 350 are sealed by the first insulator 382 and the secondinsulator 385, and are protected against electrostatic discharge byusing the conductive shield 395 provided on the outer sides of the firstinsulator 382 and the second insulator 385 which correspond to thesurface and back surface of the semiconductor device and on the sidesurfaces.

The semiconductor device which is formed in this embodiment can be usedas a flexible semiconductor device by using flexible insulators.

The conductive shield 395 transmits an electromagnetic wave that theconductive layer 380 which is an antenna included in the semiconductordevice should send and receive, and external static electricity isprevented from being applied to the semiconductor integrated circuit 350in the semiconductor device. The conductive shield 395 diffuses anddissipates static electricity applied by electrostatic discharge orprevents local existence (localization) of charge (not to generate localpotential difference); therefore, electrostatic breakdown of thesemiconductor integrated circuit 350 can be prevented.

Since the insulator and the conductive shield between which thesemiconductor integrated circuit is sandwiched are provided, an adverseeffect such as damage or deterioration of characteristics of thesemiconductor integrated circuit due to the external stress or anelectrostatic discharge can be prevented even in a manufacturingprocess. Accordingly, a semiconductor device can be formed with highyield.

With the use of the conductive shield covering a semiconductorintegrated circuit, electrostatic breakdown (malfunctions of the circuitor damages of a semiconductor element) due to electrostatic discharge ofthe semiconductor integrated circuit is prevented. Further, by using apair of insulators between which the semiconductor integrated circuit issandwiched, a highly reliable semiconductor device that is reduced inthickness and size and has tolerance can be provided. In addition,defective shapes and defective characteristics due to the externalstress or an electrostatic discharge are prevented in the manufacturingprocess, so that a semiconductor device can be manufactured with highyield. In addition, a semiconductor device can be formed with highproductivity at low cost because a plating method is used for theformation of the conductive shield.

Note that this embodiment can be implemented in combination with any ofEmbodiments 1 to 6, as appropriate.

Embodiment 8

In this embodiment, an example of a semiconductor device having higherreliability will be described. Specifically, as examples of thesemiconductor device, examples of a microprocessor and a semiconductordevice which has an arithmetic function and can send and receive datawithout contact are described.

FIG. 12 illustrates a structure of a microprocessor 500 as an example ofa semiconductor device. The microprocessor 500 is manufactured using thesemiconductor device of the above embodiment. This microprocessor 500has an arithmetic logic unit (also referred to as an ALU) 501, an ALUcontroller 502, an instruction decoder 503, an interrupt controller 504,a timing controller 505, a register 506, a register controller 507, abus interface (Bus I/F) 508, a read only memory (ROM) 509, and a memoryinterface (ROM I/F) 510.

An instruction input to the microprocessor 500 through the bus interface508 is input to the instruction decoder 503 and decoded. Then, theinstruction is input to the ALU controller 502, the interrupt controller504, the register controller 507, and the timing controller 505. The ALUcontroller 502, the interrupt controller 504, the register controller507, and the timing controller 505 perform various controls based on thedecoded instruction. Specifically, the ALU controller 502 generates asignal for controlling the operation of the arithmetic logic unit 501.The interrupt controller 504 judges an interrupt request from anexternal input/output device or a peripheral circuit based on itspriority or a mask state, and processes the request while a program isexecuted in the microprocessor 500. The register controller 507generates an address of the register 506, and reads/writes data from/tothe register 506 in accordance with the state of the microprocessor. Thetiming controller 505 generates signals for controlling timing ofdriving the arithmetic logic unit 501, the ALU controller 502, theinstruction decoder 503, the interrupt controller 504, and the registercontroller 507. For example, the timing controller 505 is provided withan internal clock generator for generating an internal clock signal CLK2based on a reference clock signal CLK1, and supplies the clock signalCLK2 to each of the above circuits. Note that the microprocessor 500illustrated in FIG. 12 is just an example of the simplified structure,and practical microprocessors have various structures depending onusage.

Next, an example of a semiconductor device which has an arithmeticfunction and can send and receive data without contact is described withreference to FIG. 13. FIG. 13 illustrates an example of a computer(hereinafter also referred to as an RFCPU) which sends and receivessignals to/from an external device by wireless communication. An RFCPU511 has an analog circuit portion 512 and a digital circuit portion 513.The analog circuit portion 512 includes a resonance circuit 514 having aresonant capacitor, a rectifier circuit 515, a constant voltage circuit516, a reset circuit 517, an oscillator circuit 518, a demodulationcircuit 519, a modulation circuit 520, and a power supply controlcircuit 530. The digital circuit portion 513 includes an RF interface521, a control register 522, a clock controller 523, an interface 524, acentral processing unit 525, a random access memory 526, and a read onlymemory 527.

The operation of the RFCPU 511 having such a structure is roughlydescribed below. The resonance circuit 514 generates inducedelectromotive force based on a signal received at an antenna 528. Theinduced electromotive force is stored in a capacitor portion 529 via therectifier circuit 515. The capacitor portion 529 is preferably formedusing a capacitor such as a ceramic capacitor or an electric doublelayer capacitor. The capacitor portion 529 is not necessarily formedover the same substrate as the RFCPU 511 and may be attached as anothercomponent to a substrate having an insulating surface over which theRFCPU 511 is formed.

The reset circuit 517 generates a signal that resets the digital circuitportion 513 to be initialized. For example, a signal which rises with adelay to a rise of the power source voltage is generated as a resetsignal. The oscillator circuit 518 changes the frequency and the dutyratio of a clock signal in accordance with a control signal generated bythe constant voltage circuit 516. The demodulation circuit 519 having alow pass filter, for example, binarizes changes in amplitude ofreception signals of an amplitude shift keying (ASK) system. Themodulation circuit 520 changes the amplitude of transmission signals ofan amplitude shift keying (ASK) system to be sent. The modulationcircuit 520 changes the resonance point of the resonance circuit 514,thereby changing the amplitude of communication signals. The clockcontroller 523 generates a control signal for changing the frequency andthe duty ratio of the clock signal in accordance with the power supplyvoltage or current consumption in the central processing unit 525. Thepower supply voltage is monitored by a power supply control circuit 530.

A signal that is input to the RFCPU 511 from the antenna 528 isdemodulated by the demodulation circuit 519, and then divided into acontrol command, data, and the like by the RF interface 521. The controlcommand is stored in the control register 522. The control commandincludes reading of data stored in the read only memory 527, writing ofdata to the random access memory 526, an arithmetic instruction to thecentral processing unit 525, and the like. The central processing unit525 accesses the read only memory 527, the random access memory 526, andthe control register 522 via the interface 524. The interface 524 has afunction of generating an access signal for any one of the read onlymemory 527, the random access memory 526, and the control register 522based on an address requested by the central processing unit 525.

As an arithmetic method of the central processing unit 525, a method maybe employed in which the read only memory 527 stores an OS (operatingsystem) and a program is read at the time of starting operation and thenexecuted. Alternatively, a method in which a circuit dedicated toarithmetic is formed and an arithmetic process is conducted usinghardware may be employed. In a method in which both hardware andsoftware are used, a method can be employed in which part of process isconducted in the circuit dedicated to arithmetic and the other part ofthe arithmetic process is conducted by the central processing unit 525using a program.

Also in the microprocessor in this embodiment, with the use of theconductive shield covering a semiconductor integrated circuit,electrostatic breakdown (malfunctions of the circuit or damages of asemiconductor element) due to electrostatic discharge of thesemiconductor integrated circuit is prevented. Further, by using a pairof insulators between which the semiconductor integrated circuit issandwiched, a highly reliable semiconductor device that is reduced inthickness and size and has tolerance can be provided. In addition,defective shapes and defective characteristics due to the externalstress or an electrostatic discharge are prevented in the manufacturingprocess, so that a semiconductor device can be manufactured with highyield. In addition, a semiconductor device can be formed with highproductivity at low cost because a plating method is used for theformation of the conductive shield.

Embodiment 9

In this embodiment, examples of usage modes of the semiconductor devicedescribed in the above embodiment will be described. Specifically, anapplication example of a semiconductor device to/from which data can beinput/output without contact is described with reference to drawings.The semiconductor device which can input and output data without contactis also referred to as an RFID tag, an ID tag, an IC tag, an RF tag, awireless tag, an electronic tag, or a wireless chip depending onapplication modes.

One example of a top structure of a semiconductor device described inthis embodiment is described with reference to FIG. 21A. A semiconductordevice illustrated in FIG. 21A includes a semiconductor integratedcircuit chip 400 having an antenna (also referred to as an on-chipantenna) and a supporting substrate 406 provided with an antenna 405(also referred to as a booster antenna). The semiconductor integratedcircuit chip 400 is provided over an insulating layer 410 formed overthe supporting substrate 406 and the antenna 405. The semiconductorintegrated circuit chip 400 can be fixed to the supporting substrate 406and the antenna 405 by using the insulating layer 410. Note that whenthe conductive shield provided on a surface of the semiconductorintegrated circuit chip 400 has high resistance and the starting pointand the ending point of the pattern of the antenna 405 under thesemiconductor integrated circuit chip 400 are not electrically connectedto each other, the antenna 405 and the conductive shield provided on thesurface of the semiconductor integrated circuit chip 400 may be providedin contact with each other.

A plurality of elements, such as transistors, which forms a memoryportion or a logic portion in a semiconductor integrated circuitprovided in the semiconductor integrated circuit chip 400, is provided.As a semiconductor element in a semiconductor device according to thisembodiment, not only a field-effect transistor, but also a memoryelement which uses a semiconductor layer can be employed; accordingly, asemiconductor device which can meet functions required for variousapplications can be manufactured and provided.

In FIG. 20A, an expansion diagram of the antenna and the semiconductorintegrated circuit included in the semiconductor integrated circuit chip400 illustrated in FIG. 21A is illustrated. In FIG. 20A, the antenna 101is a rectangular loop antenna in which the number of windings is 1;however, an embodiment of the present invention is not limited to thisstructure. The shape of the loop antenna is not limited to a rectangleand may be a shape with curve, for example, a circle. In addition, thenumber of windings is not limited to 1 and may be plural. However, whenthe number of windings of the antenna 101 is 1, parasitic capacitancegenerated between the semiconductor integrated circuit 100 and theantenna 101 can be reduced.

In FIG. 21A and FIG. 20A, the antenna 101 is placed to surround theperiphery of the semiconductor integrated circuit 100, and except for aportion corresponding to a feeding point 408 illustrated by dashedlines, the antenna 101 is arranged in a region not overlapped with thesemiconductor integrated circuit 100. However, an embodiment of thepresent invention is not limited to this structure. As illustrated inFIG. 20B, in the portion other than a portion corresponding to thefeeding point 408 illustrated by the dashed lines, at least part of theantenna 101 may be arranged to overlap the semiconductor integratedcircuit 100. However, as illustrated in FIG. 21A and FIG. 20A, since theantenna 101 is arranged in region that is different from the regionwhere the semiconductor integrated circuit 100 is provided, theparasitic capacitance generated between the semiconductor integratedcircuit 100 and the antenna 101 can be reduced.

In FIG. 21A, the antenna 405 can send and receive a signal or supplypower by using the antenna 101 and electromagnetic induction mainly in aloop-shaped portion surrounded by a dashed line 407. In addition, theantenna 405 can send and receive a signal to/from an interrogator orsupply power by using a radio wave mainly in a region other than aportion surrounded by the dashed line 407. Between the interrogator andthe semiconductor device, a frequency of a radio wave used as a carrier(a carrier wave) is preferably greater than or equal to about 30 MHz andless than or equal to about 5 GHz, for example, a frequency band such as950 MHz or 2.45 GHz may be used.

The antenna 405 is a rectangular loop antenna in which the number ofwindings is 1 in the portion surrounded by the dashed line 407; however,an embodiment of the present invention is not limited to this structure.The shape of the loop antenna is not limited to a rectangle and may be ashape with curve, for example, a circle. In addition, the number ofwindings is not limited to 1 and may be plural.

For the semiconductor device of an embodiment of the present invention,an electromagnetic induction method, an electromagnetic coupling method,or a microwave method can be employed. In the case of a microwavemethod, the shapes of the antenna 101 and the antenna 405 may bedetermined as appropriate depending on the wavelength of anelectromagnetic wave.

For example, in the case of employing a microwave method (for example, aUHF band (from 860 MHz band to 960 MHz band), a 2.45 GHz band, or thelike) as the signal transmission method in the semiconductor device, thelength, shape, and the like of the antenna may be set as appropriate inconsideration of a wavelength of an electromagnetic wave used for signaltransmission. For example, each of the antennas can be formed into alinear shape (e.g., a dipole antenna) or a flat shape (e.g., a patchantenna or an antenna having a ribbon shape). Further, each of theantennas is not limited to a linear shape and may have a curved shape, aserpentine curved shape, or in a shape combining them in considerationof the wavelength of the electromagnetic wave.

An example in which the antenna 101 and the antenna 405 have coil shapesand an electromagnetic induction method or an electromagnetic couplingmethod is used is illustrated in FIG. 10.

In FIG. 10, the semiconductor integrated circuit chip 400 having thecoiled antenna 101 is formed over the supporting substrate 406 providedwith the coiled antenna 405 as a booster antenna. Note that thesupporting substrate 406 is sandwiched between the antenna 405 which isa booster antenna, and a capacitor is formed.

Next, a structure of the semiconductor integrated circuit chip 400 andthe booster antenna, and arrangement thereof are described. FIG. 21Bcorresponds to a perspective view of the semiconductor deviceillustrated in FIG. 21A in which the semiconductor integrated circuitchip 400 and the antenna 405 formed over the supporting substrate 406are stacked. FIG. 21C corresponds to a cross-sectional view taken alonga dashed line X-Y of FIG. 21B.

The semiconductor device described in any of Embodiments 1 to 6 can beused for the semiconductor integrated circuit chip 400 illustrated inFIG. 21C, and here, semiconductor devices which are individually dividedinto chip shapes are referred to as semiconductor integrated circuitchips. Note that the semiconductor integrated circuit chip illustratedin FIG. 21C is an example using Embodiment 1; however, this embodimentcan be applied to another embodiment, and an embodiment of the presentinvention is not limited to this structure.

The semiconductor integrated circuit 100 illustrated in FIG. 21C issandwiched between the first insulator 112 and the second insulator 102,and the side surface is also sealed. In this embodiment, a firstinsulator and a second insulator between which a plurality ofsemiconductor integrated circuits is sandwiched are attached, and thenthe semiconductor integrated circuits are individually divided intostacks. A conductive shield is formed by a plating method each for thedivided stacks, and the semiconductor integrated circuit chips 400 areformed. There is no particular limitation on a separation means as longas physical separation is possible, and separation is performed by laserbeam irradiation in this embodiment.

The semiconductor device of an embodiment of the present inventionincludes the conductive shield 140 which is provided on outer sides of apair of insulators between which an antenna and a semiconductorintegrated circuit that is electrically connected to the antenna aresandwiched (on the sides where the semiconductor integrated circuit isnot provided), and side surfaces of the stack. The conductive shield 140transmits an electromagnetic wave that the antenna included in thesemiconductor device should send and receive and prevents externalstatic electricity from being applied to the semiconductor integratedcircuit in the semiconductor device.

In FIG. 21C, the semiconductor integrated circuit 100 is closer to theantenna 405 than the antenna 101; however an embodiment of the presentinvention is not limited to this structure. The antenna 101 may becloser to the antenna 405 than the semiconductor integrated circuit 100.The semiconductor integrated circuit 100 and the antenna 101 may bedirectly attached to the first insulator 112 and the second insulator102, or may be attached by a bonding layer functioning as an adhesive.

Next, an operation example of the semiconductor device of thisembodiment is described. FIG. 19 is a block diagram illustrating anexample of a structure of a semiconductor device of this embodiment. Asemiconductor device 420 illustrated in FIG. 19 has an antenna 422 whichis a booster antenna, a semiconductor integrated circuit 423, and anantenna 424 which is an on-chip antenna. When an electromagnetic wave issent from an interrogator 421, the antenna 422 receives theelectromagnetic wave, whereby alternating current is generated in theantenna 422 and a magnetic field is generated around the antenna 422.Then, a loop-shaped portion included in the antenna 422 and the antenna424 having a loop shape are electromagnetically coupled, and inducedelectromotive force is generated in the antenna 424. The semiconductorintegrated circuit 423 receives a signal or power from the interrogator421 by using the induced electromotive force. On the other hand, currentflows into the antenna 424 and induced electromotive force is generatedin the antenna 422 in accordance with a signal generated in thesemiconductor integrated circuit 423, whereby a signal can be sent tothe interrogator 421 using a reflected wave of the radio wave that issent from the interrogator 421.

Note that the antenna 422 is divided into a loop-shaped portion in whichelectromagnetic coupling is mainly performed between the antenna 422 andthe antenna 424, and a portion in which a radio wave from theinterrogator 421 is mainly received. The shape of the antenna 422 in theportion in which an electric wave from the interrogator 421 is mainlyreceived may be a shape in which an electric wave can be received. Forexample, shapes such as a dipole antenna, a folded-dipole antenna, aslot antenna, a meander line antenna, or a microstrip antenna may beused.

In FIGS. 21A to 21C, structures of the semiconductor integrated circuiteach including only one antenna are illustrated; however, an embodimentof the present invention is not limited to this structure. Two antennas,that is, an antenna for receiving power and an antenna for receiving asignal may be included. If two antennas are provided, frequency of aradio wave for supplying power and frequency of a radio wave for sendinga signal can be separately used.

In a semiconductor device of this embodiment, the on-chip antenna isused and a signal or power can be sent and received between the boosterantenna and the on-chip antenna without contact; therefore, unlike thecase where a semiconductor integrated circuit is connected to anexternal antenna, the semiconductor integrated circuit and the antennaare less likely to be disconnected due to external force, and generationof initial failure in the connection can also be suppressed. Unlike thecase where only an on-chip antenna is used, the booster antenna is alsoused in this embodiment. Therefore, the advantage of the externalantenna can be enjoyed, for example, a dimension or shape of the on-chipantenna is less likely to be affected by restriction of the area of thesemiconductor integrated circuit, a frequency band of radio wave whichcan be received is not limited, and communication distance can beextended.

In the semiconductor device to which an embodiment of the presentinvention is applied, with the use of the conductive shield covering asemiconductor integrated circuit, electrostatic breakdown (malfunctionsof the circuit or damages of a semiconductor element) due toelectrostatic discharge of the semiconductor integrated circuit isprevented. Further, by using a pair of insulators between which thesemiconductor integrated circuit is sandwiched, a highly reliablesemiconductor device that is reduced in thickness and size and hastolerance can be provided. In addition, defective shapes and defectivecharacteristics due to the external stress or an electrostatic dischargeare prevented in the manufacturing process, so that a semiconductordevice can be manufactured with high yield. In addition, a semiconductordevice can be formed with high productivity at low cost because aplating method is used for the formation of the conductive shield.Therefore, an embodiment of the present invention is effective in thecase of a small semiconductor device to/from which data can beinput/output without contact as described in this embodiment. Since thesemiconductor device of this embodiment has high reliability withrespect to external force, environmental conditions under which thesemiconductor device can be used can be varied; thus, greaterversatility of the semiconductor device can be achieved.

Embodiment 10

In this embodiment, an example of application of the above semiconductordevice which can input and output data without contact, which is formedusing an embodiment of the present invention, will be described. Thesemiconductor device which can input and output data without contact isalso referred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RFtag, a wireless tag, an electronic tag, or a wireless chip depending onapplication modes.

A semiconductor device 800, which has a function in which data can beexchanged without contact, includes a high frequency circuit 810, apower supply circuit 820, a reset circuit 830, a clock generator circuit840, a data demodulation circuit 850, a data modulation circuit 860, acontrol circuit 870 used for controlling other circuits, a memorycircuit 880, and an antenna 890 (see FIG. 11A). The high-frequencycircuit 810 receives a signal from the antenna 890 and outputs a signal,which is received from the data modulation circuit 860, with the antenna890. The power supply circuit 820 generates power source potential froma received signal. The reset circuit 830 generates a reset signal. Theclock generator circuit 840 generates various clock signals based on areceived signal input from the antenna 890. The data demodulationcircuit 850 demodulates a received signal and outputs the demodulatedsignal to the control circuit 870. The data modulation circuit 860modulates a signal received from the control circuit 870. As the controlcircuit 870, for example, a code extracting circuit 910, a code judgingcircuit 920, a CRC judging circuit 930, and an output unit circuit 940are provided. Note that the code extracting circuit 910 extracts each ofa plurality of codes included in an instruction sent to the controlcircuit 870. The code judging circuit 920 judges the content of theinstruction by comparing the extracted code with a code corresponding toa reference. The CRC judging circuit 930 detects whether or not there isa transmission error or the like based on the judged code.

Next, an example of operation of the above semiconductor device will bedescribed. First, a radio signal is received by the antenna 890. Theradio signal is sent to the power supply circuit 820 via thehigh-frequency circuit 810, and a high power source potential(hereinafter referred to as VDD) is generated. The VDD is supplied toeach circuit in the semiconductor device 800. A signal sent to the datademodulation circuit 850 through the high-frequency circuit 810 isdemodulated (hereinafter, this signal is referred to as a demodulatedsignal). Moreover, signals and demodulated signals passed through thereset circuit 830 and the clock generator circuit 840 through thehigh-frequency circuit 810, and the demodulated signal are sent to thecontrol circuit 870. The signals sent to the control circuit 870 areanalyzed by the code extracting circuit 910, the code judging circuit920, the CRC judging circuit 930, and the like. Then, based on theanalyzed signals, information of the semiconductor device stored in thememory circuit 880 is output. The output information of thesemiconductor device is encoded through the output unit circuit 940.Further, the encoded information of the semiconductor device 800 passesthrough the data modulation circuit 860 and then is sent by the antenna890 as a wireless signal. Note that low power source potential(hereinafter referred to as VSS) is common in the plurality of circuitsincluded in the semiconductor device 800, and VSS can be GND.

In this manner, data of the semiconductor device can be read by sendinga signal to the semiconductor device 800 from a communication device andby receiving a signal which is sent from the semiconductor device 800 bythe communication device.

Moreover, in the semiconductor device 800, power source voltage may besupplied to each circuit by electromagnetic waves without mounting apower source (battery), or a power source (battery) may be mounted sothat power source voltage is supplied to each circuit by bothelectromagnetic waves and the power source (battery).

Next, an example of usage of a semiconductor device in which data can beinput/output without contact is described. A side surface of a mobileterminal which includes a display portion 3210 is provided with acommunication device 3200. A side surface of a product 3220 is providedwith a semiconductor device 3230 (FIG. 11B). When the communicationdevice 3200 is held up to the semiconductor device 3230 included in theproduct 3220, the display portion 3210 displays information about theproduct, such as its materials, its place of production, inspectionresults for each production step, a history of the distribution process,and a description of the product. Further, when a product 3260 isconveyed by a conveyer belt, the product 3260 can be inspected by usinga communication device 3240 and a semiconductor device 3250 with whichthe product 3260 is provided (FIG. 11C). In this manner, information canbe easily obtained, and high functions and high added values arerealized by utilizing a semiconductor device for a system.

Thus, a highly reliable semiconductor device according to an embodimentof the present invention, which has a very wide range of application,can be used in electronic devices in a variety of fields.

Embodiment 11

According to an embodiment of the present invention, a semiconductordevice functioning as a chip having a processor circuit (hereinafteralso called a processor chip, a wireless chip, a wireless processor, awireless memory, or a wireless tag) or an RFID tag can be formed. Theapplication range of the semiconductor device of an embodiment of thepresent invention is so wide that it may be applied to any object inorder that the history thereof is revealed wirelessly and utilized inproduction, management, and the like. For example, the semiconductordevice of an embodiment of the present invention may be incorporated inbills, coins, securities, certificates, bearer bonds, packagingcontainers, books, recording media, personal belongings, vehicles,groceries, garments, health products, daily commodities, medicines, andelectronic devices. These examples are described with reference to FIGS.9A to 9G.

The bills and coins are money that circulates in the market, andincludes one that can be used in the same way as money in a specificarea (cash voucher), a commemorative coin, and the like. The securitiesinclude checks, certificates, promissory notes, and the like, and can beprovided with a chip 190 including an RFID tag (see FIG. 9A). Thecertificates refer to driver's licenses, certificates of residence, andthe like, and can be provided with a chip 191 including an RFID tag (seeFIG. 9B). The personal belongings include bags, a pair of glasses, andthe like, and can be provided with a chip 197 including an RFID tag (seeFIG. 9C). Bearer bonds refer to stamps, rice coupons, variousmerchandise coupons, and the like. Packing containers refer to wrappingpaper for food containers, plastic bottles, and the like and can beprovided with a chip 193 including an RFID tag (see FIG. 9D). The booksrefer to hardbacks, paperbacks, and the like, and can be provided with achip 194 including an RFID tag (see FIG. 9E). The recording media referto DVD software, video tapes, and the like, and can be provided with achip 195 including an RFID tag (see FIG. 9F). Vehicles refer to wheeledvehicles such as bicycles, ships, and the like, and can be provided witha chip 196 including an RFID tag (see FIG. 9G). The groceries indicatefoods, beverages, and the like. The garments indicate clothes, shoes,and the like. The health products indicate a medical apparatus, a healthappliance, and the like. The daily commodities indicate furniture,lighting apparatus, and the like. The medicines indicate a medicalproduct, an agricultural chemical, and the like. The electronic devicesindicate a liquid crystal display device, an EL display device,television sets (a television receiver and a thin television receiver),a cellular phone, and the like.

The semiconductor device can be provided by being attached to thesurface of an article or being embedded in an article. For example, inthe case of a book, the semiconductor device may be embedded in thepaper; and in the case of a package made of an organic resin, thesemiconductor device may be embedded in the organic resin.

As described above, the efficiency of an inspection system, a systemused in a rental shop, or the like can be improved by providing thepacking containers, the recording media, the personal belonging, thegroceries, the garments, the daily commodities, the electronic devices,or the like with the semiconductor device. In addition, by providing thevehicles with the semiconductor device, forgery or theft can beprevented. In addition, when the semiconductor device is implanted intocreatures such as animals, each creature can be identified easily. Forexample, by attaching the semiconductor device with a sensor to acreature such as livestock, its health condition such as a current bodytemperature as well as its birth year, sex, breed, or the like can beeasily managed.

Note that this embodiment can be implemented in combination with any ofEmbodiments 1 to 9, as appropriate.

Embodiment 12

In this embodiment, an example of mounting a semiconductor device of anembodiment of the present invention will be described with reference toFIGS. 18A to 18D.

The semiconductor device of an embodiment of the present invention canbe mounted on an article as described in Embodiment 9. In thisembodiment, an example in which a flexible semiconductor device mountedon a flexible substrate is formed is described.

FIGS. 18A to 18C are each an example in which a semiconductor integratedcircuit chip is embedded in flexible substrates. The semiconductordevice described in Embodiments 1 to 6 can be used for the semiconductorintegrated circuit chip, and here, semiconductor devices which areindividually divided into chip shapes are referred to as semiconductorintegrated circuit chips. A semiconductor integrated circuit chip 600 isillustrated in detail in FIG. 18D. The semiconductor integrated circuitchip of FIG. 18D is an example using Embodiment 1; however, thisembodiment can be applied to another embodiment, and an embodiment isnot limited to this structure.

In FIG. 18D, the antenna 101 and the semiconductor integrated circuit100 are sandwiched between the first insulator 112 and the secondinsulator 102, and the side surfaces of a stack are also sealed. In thisembodiment, a plurality of semiconductor integrated circuits issandwiched between the first insulator 112 and the second insulator 102,and then the semiconductor integrated circuit is individually dividedinto semiconductor integrated circuit chips each including the antenna101 and the semiconductor integrated circuit 100, whereby thesemiconductor integrated circuit chips are formed. There is noparticular limitation on a separation means as long as physicalseparation is possible, and separation is performed by laser beamirradiation in this embodiment.

The antenna 101 and the semiconductor integrated circuit 100 are sealedby the first insulator 112 and the second insulator 102 by separation,and divided surfaces are generated as side surfaces of a chip. Theconductive shield 140 is formed by a plating method to surround theperiphery of a divided semiconductor integrated circuit chip.

Accordingly, the antenna 101 and the semiconductor integrated circuit100 are sealed by the first insulator 112 and the second insulator 102,and are protected against electrostatic discharge by using theconductive shield 140 provided on the outer sides of the first insulator112 and the second insulator 102 which correspond to the surface andback surface of the semiconductor device and on the side surfaces of thestack.

With the use of the conductive shield covering a semiconductorintegrated circuit, electrostatic breakdown (malfunctions of the circuitor damages of a semiconductor element) due to electrostatic discharge ofthe semiconductor integrated circuit is prevented. Further, by using apair of insulators between which the semiconductor integrated circuit issandwiched, a highly reliable semiconductor device that is reduced inthickness and size and has tolerance can be provided. In addition,defective shapes and defective characteristics due to the externalstress or an electrostatic discharge are prevented in the manufacturingprocess, so that a semiconductor device can be manufactured with highyield.

In FIG. 18A, the semiconductor integrated circuit chip 600 is sandwichedbetween a flexible substrate 601 and a flexible substrate 602, and thesemiconductor integrated circuit chip 600 is provided in a depressedportion formed in the flexible substrate 601.

The depressed portion in which the semiconductor integrated circuit chip600 is provided may be formed in one flexible substrate or may be formedin both flexible substrates. In FIG. 18B, an example is illustrated inwhich the semiconductor integrated circuit chip 600 is provided in thedepressed portions provided in both the flexible substrate 601 and theflexible substrate 602.

Further, three flexible substrates may be used and a central flexiblesubstrate may be provided with an opening in which the semiconductorintegrated circuit chip 600 is provided. In FIG. 18C, an example isillustrated in which an opening is formed in a flexible substrate 603,the semiconductor integrated circuit chip 600 is provided in theopening, and the flexible substrate 603 and the semiconductor integratedcircuit chip 600 are sandwiched between the flexible substrate 601 andthe flexible substrate 602.

In FIGS. 18A to 18C, a flexible substrate may be stacked on an outerside (outer sides) of the flexible substrate 601 and/or the flexiblesubstrate 602.

For each of the flexible substrates 601, 602, and 603, a woven fabricwhich is woven using bundles of fibers (single yarns) (hereinafter, thebundles of fibers are referred to as yarn bundles) for warp yarns andweft yarns, a nonwoven fabric obtained by stacking yarn bundles ofplural kinds of fibers randomly or in one direction, paper, or the likecan be used. Specifically, the following can be used: a substrate formedfrom polyethylene terephthalate (PET), polyethylene naphthalate (PEN),polyethersulfone (PES), polypropylene, polypropylene sulfide,polycarbonate, polyetherimide, polyphenylene sulfide, polyphenyleneoxide, polysulfone, polyphthalamide, or the like; a substrate formedfrom polypropylene, polyester, vinyl, polyvinyl fluoride, vinylchloride, polyester, polyamide, or the like; a film; paper formed from afibrous material; and the like. A layered film of an adhesive syntheticresin film (such as an acrylic synthetic resin or an epoxy syntheticresin), or the like can be used. When a substrate or a film is bonded toa subject to be processed, a bonding layer may be used. A condition canbe selected in accordance with the kind of the substrate or the film,and bonding can be performed by heat treatment or application ofpressure. A bonding layer corresponds to a layer containing an adhesivesuch as a thermosetting resin, a UV curing resin, an epoxy resinadhesive, or a resin additive.

As in this embodiment, when a depressed portion or an opening is formedin a flexible substrate on which a semiconductor integrated circuit chipis mounted and the semiconductor integrated circuit chip 600 is providedso as to be embedded in the depressed portion or the opening, aprojected portion is not formed due to the provision of thesemiconductor integrated circuit chip 600; therefore, the surface of theflexible substrate is flat, and film thickness can be uniform.Accordingly, even if pressure treatment is performed with a roller orthe like for attachment when a semiconductor integrated circuit chip ismounted on a flexible substrate, pressure can be prevented from beinglocally applied on the semiconductor integrated circuit chip (pressureconcentration). Therefore, damages of the semiconductor integratedcircuit chip can be reduced in a mounting step, whereby the yield of asemiconductor device is improved. In addition, even after asemiconductor integrated circuit chip is mounted, a highly reliablesemiconductor device which has high tolerance to external stress can beformed.

In addition, since a surface can be flat and smooth, stacking overmachine, storage, transferring, and the like are easily performed.Further, a semiconductor integrated circuit chip is not visuallyidentified from the outside (a projected portion that reflects a shapeof the semiconductor integrated circuit chip is not generated on thesurface); therefore, a semiconductor device with high security can beformed.

This application is based on Japanese Patent Application serial No.2008-149603 filed with Japan Patent Office on Jun. 6, 2008, the entirecontents of which are hereby incorporated by reference.

1. A method for manufacturing a semiconductor device comprising thesteps of: forming a semiconductor integrated circuit and an antennaelectrically connected to the semiconductor integrated circuit;sandwiching the semiconductor integrated circuit and the antenna betweena first insulator and a second insulator which are provided to face eachother; and forming, by a wet plating method, at least two conductiveshields electrically connected to each other on surfaces of the firstinsulator and the second insulator, on the surfaces of which thesemiconductor integrated circuit is not formed.
 2. The method formanufacturing the semiconductor device according to claim 1, whereinnickel alloy films or copper films are formed as the conductive shields.3. The method for manufacturing the semiconductor device according toclaim 1, wherein a structure body in which a fibrous body is impregnatedwith an organic resin is used for at least one of the first insulatorand the second insulator.
 4. A method for manufacturing a semiconductordevice comprising the steps of: forming a semiconductor integratedcircuit and an antenna electrically connected to the semiconductorintegrated circuit; sandwiching the semiconductor integrated circuit andthe antenna between a first insulator and a second insulator which areprovided to face each other; and immersing a stack of the semiconductorintegrated circuit, the antenna, the first insulator, and the secondinsulator in a plating solution including a conductive material to forma conductive shield covering surfaces of the stack.
 5. The method formanufacturing the semiconductor device according to claim 4, wherein anickel alloy film or a copper film is formed as the conductive shield.6. The method for manufacturing the semiconductor device according toclaim 4, wherein a structure body in which a fibrous body is impregnatedwith an organic resin is used for at least one of the first insulatorand the second insulator.
 7. A method for manufacturing a semiconductordevice comprising the steps of: forming a semiconductor integratedcircuit and an antenna electrically connected to the semiconductorintegrated circuit; sandwiching the semiconductor integrated circuit andthe antenna between a first insulator and a second insulator which areprovided to face each other; immersing a stack of the semiconductorintegrated circuit, the antenna, the first insulator, and the secondinsulator in a solution including a catalyst material, and making thecatalyst material adsorbed on surfaces of the stack; and immersing thestack to which the catalyst material is adsorbed in a plating solutionincluding a conductive material to form a conductive shield covering thesurfaces of the stack to which the catalyst material is adsorbed.
 8. Themethod for manufacturing the semiconductor device according to claim 7,wherein palladium is used as the catalyst material.
 9. The method formanufacturing the semiconductor device according to claim 7, wherein anickel alloy film or a copper film is formed as the conductive shield.10. The method for manufacturing the semiconductor device according toclaim 7, wherein a structure body in which a fibrous body is impregnatedwith an organic resin is used for at least one of the first insulatorand the second insulator.
 11. A method for manufacturing a semiconductordevice comprising the steps of: forming a semiconductor integratedcircuit and an antenna electrically connected to the semiconductorintegrated circuit; sandwiching the semiconductor integrated circuit andthe antenna between a first surface of first insulator and a firstsurface of a second insulator so that a second surface of the firstinsulator and a second surface of the second insulator are outside; andforming a first conductive shield on the second surface of the firstinsulator and a second conductive shield on the second surface of thesecond insulator by a wet plating method, wherein the first conductiveshield and the second conductive shield are electrically connected toeach other.
 12. The method for manufacturing the semiconductor deviceaccording to claim 11, wherein nickel alloy films or copper films areformed as the conductive shields.
 13. The method for manufacturing thesemiconductor device according to claim 11, wherein a structure body inwhich a fibrous body is impregnated with an organic resin is used for atleast one of the first insulator and the second insulator.